Abstract: An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation.

Abstract: According to one embodiment, a memory system includes a data manager and a data restorer. The data manager multiplexes difference logs by a parallel writing operation and stores them in a second storage area, the difference logs being difference logs indicating difference information before and after update of a management table; and thereafter multiplexes predetermined data as finalizing logs and stores them in the second storage area. The data restorer determines a system status at startup of the memory system, by judging whether irregular power-off occurs or data destruction occurs in the second storage area, based on a data storage state of the difference logs and the finalizing logs stored in the second storage area.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: Errors arising in logical volume partitions are detected and corrected automatically well before the errors cause a failure to access data. A database is created of configuration information about the logical volume partitions defined in physical volume headers, and the database is stored in storage separate from the headers. Thereafter the errors are detected by capturing configuration information about the logical volume partitions from the headers, and comparing the captured configuration information to the configuration information in the database. The errors are automatically corrected in the corrupt headers. If requested, a report is generated of the volumes and disk partitions that are inaccessible or missing or have the wrong size. The configuration check is performed periodically as a background task and during a re-boot after a system crash or interruption of a configuration process or when invoked prior to a recovery install or database restore.

Abstract: A method of transmitting an acknowledgment (ACK)/non-acknowledgement (NACK) signal in a wireless communication system includes assigning at least one ACK channel among a plurality of ACK channels which share an ACK channel region for transmitting the ACK/NACK signal, and transmitting the ACK/NACK signal through the at least one ACK channel, wherein the ACK channel region includes at least one tile including a plurality of data subcarriers, and the ACK/NACK signal of each ACK channel is indicated by mapping different orthogonal vectors respectively to the plurality of ACK channels in the tile.

Abstract: Methods, media, and systems for detecting an anomalous sequence of function calls are provided. The methods can include compressing a sequence of function calls made by the execution of a program using a compression model; and determining the presence of an anomalous sequence of function calls in the sequence of function calls based on the extent to which the sequence of function calls is compressed. The methods can further include executing at least one known program; observing at least one sequence of function calls made by the execution of the at least one known program; assigning each type of function call in the at least one sequence of function calls made by the at least one known program a unique identifier; and creating at least part of the compression model by recording at least one sequence of unique identifiers.

Abstract: An apparatus and a method for detecting and reporting malfunctions in computer programs is described. A malfunction detector detects at least one type of a software malfunction as defined in a configurable malfunction library. A data collector collects data of the software malfunction. A crash reporter reports the crash report in a manner specified in a configurable reporting library corresponding to the type of software malfunction to one or more remote computers.

Abstract: In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.

Abstract: An approach is provided to trace a software program running in a multi-nodal complex computing environment. A trace request is sent from a requestor node to the nodes with the trace request associated with the software program and also associated with a transaction identifier. The software program is executed on the nodes. While the program is executing, trace data entries resulting from the execution of the software program are logged at the respective nodes with each trace data entry being associated with the transaction identifier. A log request is subsequently sent from the requestor node to the other nodes. The resulting trace data is then received by the requestor node from the target nodes and logged in a transaction based log. The transaction-based log is then provided to a user of the requestor node.

Abstract: Method and application server for providing an asynchronous error notification from an application server to an application server controller in a network is provided. The method at the application server includes generating an error message when an error occurs at/during Open Service Gateway initiative (OSGi) framework runtime. The method also includes converting the error message as a Universal Plug and Play (UPnP) event. Moreover, the method includes providing the UPnP event comprising error information to the application server controller. The application server includes a receiver configured to receive a command from an application server controller to install an application in an Open Service Gateway initiative (OSGi) framework available at the application server. The application server also includes a processor configured to generate an error message when an error occurs during installation of the application in the framework and convert the error message as a Universal Plug and Play (UPnP) event.

Abstract: A method of error control, including forming a plurality of first data symbols from a plurality of data bits, transmitting a first signal including the plurality of first data symbols, receiving a request for retransmission, forming a plurality of second data symbols from the plurality of data bits, and transmitting a second signal including the plurality of second data symbols. At least one of the first data symbols is formed from several of the plurality of data bits such that none of the second data symbols is formed from the several of the plurality of data bits.

Abstract: Exemplary system, and computer program product embodiments for optimizing disaster recovery systems during takeover operations are provided. In one embodiment, by way of example only, a flag is set in a replication grid manager to identify replication grid members to consult in a reconciliation process for resolving intersecting and non-intersecting data amongst the disaster recovery systems for a takeover operation. The replication grid members are consulted for the takeover operation to accommodate a coordination of an ownership synchronization process for cartridges not distributed on-time to the replication grid members. Additional system and computer program product embodiments are disclosed and provide related advantages.

Abstract: Methods, apparatus and articles of manufacture for controlling nanostore operation based on monitored performance are disclosed. An example method disclosed herein comprises monitoring performance of a nanostore, the nanostore including compute logic and a datastore accessible via the compute logic, and controlling operation of the nanostore in response to detecting a performance indicator associated with wearout of the compute logic to permit the compute logic to continue to access the datastore.

Abstract: A scan cell is configured to receive first, second and third data bits at respective first, second and third data inputs. A control input is configured to receive a control signal. Latching logic is configured to latch data received at the first and second latch inputs to a scan cell output. The first latch input is configured to receive the first data bit. Selection logic is configured to select between the second and third data bits depending on a state of the control signal, and to provide the selected bit to the second latch input.

Abstract: An apparatus, system, and method are disclosed for probing a computer process. A probe parameter module determines a process identifier, a probe interval, and a probe action. The process identifier uniquely identifies a computer process. A start timer module starts a timer with a timer interval in response to the computer process entering an executing state on a processor core. The timer interval is based on the probe interval and on an amount of time elapsed between a probe start time and the computer process entering the executing state on the processor core. An action module executes the probe action in response to the timer satisfying the timer interval while the computer process is in the executing state on the processor core.

Abstract: A debug card for diagnosing a motherboard and a power supply unit (PSU) of a same computer includes a plurality of first nixie tubes, a plurality of second nixie tubes, a first port, a second port, and a control unit. The control unit is electronically connected to the plurality of first nixie tubes, the plurality of second nixie tubes, the first port, and the second port. The first port is electronically connected to the motherboard, and the second port is electronically connected to the PSU. Under the control of the control unit, fault codes of the motherboard are displayed by the plurality of the first nixie tubes, and fault codes of the PSU are displayed by the plurality of the second nixie tubes.

Abstract: Each of SAS expanders (“expander(s)” hereinafter) has a switch device for switching whether to bypass the expander in each communication path or not. Of the plurality of switch devices, an actual connection destination of a switch device bypassing the expander is a switch device in a upper-level and/or a lower-level of the switch device. Of the plurality of switch devices, an actual connection destination of a switch device that does not bypass an expander is the expander.

Abstract: The monitoring and recovery of data instances, data stores, and other such components in a data environment can be performed automatically using a separate control environment. A monitoring component of the control plane can include a set of event processors for monitoring a workload of the data environment, where an event processor detecting a problem in the data plane can cause a recovery workflow to be generated in order to recover from the detected problem. The event processors can communicate with each other such that if one of the event processors becomes unavailable, the other event processors in a set are able to automatically redistribute responsibility for the workload.

Abstract: An invention is provided for dynamically configurable error correction. The invention includes receiving a check code configuration signal, which indicates a particular level of error detection. A check code generator is configured to generate check codes based on the particular level of error detection indicated by the check code configuration signal. In addition, an error locator configuration signal is received that indicates a particular level of error addressing, and an error locator is configured to produce addresses of errors in a set of data based on the particular level of error addressing indicated by the error locator configuration signal.

Abstract: A multiple input multiple output (MIMO) iterative receiver detects a soft log likelihood ratio value from a signal outputted from a transmitter and decodes the detected soft log likelihood ratio value in order to extract a hard value and a soft value from the detected soft log likelihood ratio value. After whether or not a CRC of the hard value is acknowledged is determined, a CRC of a data burst is determined or iteration of signal demodulation of the MIMO iterative receiver is determined by feeding back the soft value or a CRC of data is performed assembling signals of the burst unit in accordance with the determination result.