Abstract: A universal serial bus (USB) device for receiving data from a link partner is provided. An electrical physical unit receives a series of data from the link partner via a cable and generates a symbol string corresponding to the series of data, wherein the symbol string includes a plurality of symbols. A correction unit receives the symbol string, determines whether each symbol of the received symbol string is a first type symbol and counts a quantity of the received first type symbol, wherein when the counted quantity is odd and a next received symbol is a second type symbol, the next received symbol is replaced with the first type symbol by the correction unit.

Abstract: A method of transmitting an acknowledgment (ACK)/non-acknowledgement (NACK) signal in a wireless communication system includes assigning at least one ACK channel among a plurality of ACK channels which share an ACK channel region for transmitting the ACK/NACK signal, and transmitting the ACK/NACK signal through the at least one ACK channel, wherein the ACK channel region includes at least one tile including a plurality of data subcarriers, and the ACK/NACK signal of each ACK channel is indicated by mapping different orthogonal vectors respectively to the plurality of ACK channels in the tile.

Abstract: An apparatus and method for transmitting and receiving symbols in a mobile communication system, in which a multiplexer and burst mapper divides each of first and second group data blocks into a plurality of sub-blocks, the symbols including the first group data block and the second group data block, the second group data block having a different priority level from the first group data block, and maps a combination of one of the first group data sub-blocks and one of the second group data sub-blocks to each burst. A modulator maps a bit of the first group data sub-block and a bit of the second group data sub-block to a symbol according to a bit reliability pattern of modulation symbols in each burst.

Abstract: A method and apparatus for conducting transition testing using scan elements are disclosed. In one embodiment, an integrated circuit (IC) includes a scan chain having first and second subsets of scannable flops, the first subset having respective data inputs coupled to a memory array. The scannable flops of the second subset may each have a respective data input coupled to circuitry other than the memory array (e.g., to a logic circuit). The scannable flops of the first subset may be enabled for scan shifting during a transition test mode. The scannable flops of the second subset are inhibited from scanning during the transition test mode. The transition test mode may include at least two functional clock cycles in which the scannable flops of the first subset provide complementary first and second logic values to logic circuits coupled to respective data outputs.

Abstract: A method of ensuring high integrity of a processor is provided. The method includes executing sets of sequential instructions, each execution being based on a unique initial value, generating a computed final value responsive to each execution of a set of sequential instructions, and sending computed values to a monitoring portion of a high integrity processor monitor system responsive to the generating for each execution of the set of sequential instructions. The execution of the sets of sequential instructions tests pertinent addressing modes, operand sizes, and instruction side-effects for each instruction tested in a monitored central processing unit.

Abstract: Systems and methods are disclosed for monitoring and managing data transactions, such as SQL transactions. In certain examples, a management subsystem generates an alert identifying degrading database transactions to facilitate preventative tuning or other maintenance. In particular, a monitor module tracks performance measurements (e.g., logical reads) of select transactions. A modeler correlates the performance measurements and assigns first performance model(s) to represent the performance measurements and predicted performance measurements of a particular transaction. A trend change module detects a significant change in a trend and/or variance of the performance measurements and can cause the modeler module to generate a second performance model to represent at least a portion of the performance measurements and the predicted performance measurements of the particular transaction.

Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header includes a CRC to provide improved error detection.

Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header includes a CRC to provide improved error detection.

Abstract: Aspects described a low receiver complexity approach for reliable packet decoding when Hybrid ARQ protocol is employed with persistent assignment and potentially an erasure sequence transmission. Multiple hypotheses packet decoding performance is achieved while mitigating multiple hypotheses receiver complexity. A reference number is utilized to perform hypotheses. The reference number is independent of a start of packet. A sequence of reference numbers can be utilized, which may not necessarily be sequential numbers. The reference numbers are pre-defined.

Abstract: A cluster comprises a plurality of nodes that access a shared storage, each node having two or more partner nodes. A primary node may own a plurality of aggregate sub-sets in the shared storage. Upon failure of the primary node, each partner node may take over ownership of an aggregate sub-set according to an aggregate failover data structure (AFDS). The AFDS may specify, an ordered data structure of two or more partner nodes to take over each aggregate sub-set, the ordered data structure comprising at least a first-ordered partner node assigned to take over the aggregate sub-set upon failure of the primary node and a second-ordered partner node assigned to take over the aggregate sub-set upon failure of the primary node and the first-ordered partner node. The additional workload of the failed primary node is distributed among two or more partner nodes and protection for multiple node failures is provided.

Abstract: Forward Error Correction (FEC) coding is performed on data packets to generate verifying packets; corresponding information independent of a packet sequence number (SN) and denoting a corresponding relation between the data packets and the verifying packets is carried in the data packets, or in the verifying packets, or in the data packets and the verifying packets; the data packets and the verifying packets are transmitted by using a protocol based on a User Datagram Protocol (UDP). A method for receiving data packets and devices for transmitting and receiving data packets are further described. Thus, a receiving terminal correctly can recover lost data packets after a relay device modifies the packet SN.

Abstract: The described embodiments provide a processor (e.g., processor 102) for executing instructions. During execution, the processor starts by transactionally executing instructions from a protected section of program code. The processor then encounters a transactional failure condition while transactionally executing the instructions from the protected section of program code. In response to encountering the transactional failure condition, the processor enters a transactional-scout mode and speculatively executes subsequent instructions in the transactional-scout mode.

Abstract: A voice activity detection (VAD) dependent retransmission scheme is described that mitigates the effect of packet loss on an audio signal transmitted between terminals in a wireless communication system in a manner that is generally more robust than conventional state-of-the art packet loss concealment algorithms but that consumes less terminal power as compared to conventional retransmission schemes. In one implementation, this is achieved by allowing retransmissions to be requested by a terminal only when a packet received by the terminal is deemed bad and when a portion of an audio signal currently being received by the terminal is deemed to comprise active speech. In other implementations, the processing of retransmission requests received by a terminal is inhibited or turned off entirely during periods when a portion of an audio signal currently being transmitted by the terminal is deemed not to comprise active speech.

Abstract: According to some embodiments, delta checkpoints are provided for a non-volatile memory indirection table to facilitate a recovery process after a power loss event.

Abstract: In a particular embodiment, a channel detector is disclosed that includes a programmable look-up table (LUT) to relate user bits to channel bits. The programmable LUT is adapted to be implemented on a state trellis of arbitrary radix. The channel detector further includes a sectional precoder coupled to a channel and having access to the programmable LUT. The sectional precoder is adapted to map channel bits to user bits and vice versa using a programmable LUT.

Abstract: A method for memory scrubbing is provided. In this method, a first resistance of a reference memory element is read. A second resistance of a memory element also is read. A difference between the first resistance and the second resistance is sensed and a programming error associated with the second resistance is detected based on the difference. Each memory element is non-volatile and re-writeable, and can be positioned in a two-terminal memory cell that is one of a plurality of memory cells positioned in a two-terminal cross-point memory array. Active circuitry for performing the memory scrubbing can be fabricated FEOL in a logic layer and one or more layers of the two-terminal cross-point memory arrays can be fabricated BEOL over the logic layer. Each memory cell can optionally include non-ohmic device (NOD) electrically in series with the memory element and the two terminals of the memory cell.

Abstract: A multi-stage decoder decodes a block of symbols, received via a noisy channel, to a codeword. The decoder includes multiple sub-decoders connected sequentially, and wherein a next sub-decoder has a slower processing time and better word error rate than a previous sub-decoder, and wherein the next sub-decoder is only executed if the previous decoder fails to decode the block sequence of symbols, and a last sub-decoder is executed until a termination condition is reached.

Abstract: A data protection method is provided. The method includes receiving data; generating compressed data based on the data; determining a degree of compressibility based on the compressed data; determining an amount of free space based on the degree of compressibility; and setting one or more error bits based on the amount of free space.

Abstract: A software component is executed to carry out a task, the task including a subtask. An external function is called to perform the subtask, the external function executing in a separate thread or process. The component receives an observation recorded by the external function, the observation including an identifier of a possible error condition and instance data associated with the possible error condition. The possible error condition being a cause of the failure of the external function to carry out the subtask. If the task cannot be completed, then a new observation is recorded along with the received observation, the new observation being related to a possible error condition of the component, which is a cause of the failure of the component to carry out the task. When the task can be completed despite the failure of the external function, the observation recorded by the external function is cleared.

Abstract: Data is processed by obtaining a length of an error locator polynomial. It is determined whether the length of the error locator polynomial is greater than a threshold. In the event the length of the error locator polynomial is greater than the threshold, performance of a Chien search on the error locator polynomial is skipped. In the event the length of the error locator polynomial is less than or equal to than the threshold, the Chien search is performed on the error locator polynomial to determine one or more roots of the error locator polynomial, where the roots correspond to one or more error locations.