Abstract: A method of testing the integrity of microprogramming within a computer processor employs a test calculation designed to exercise instructions and to reveal errors in those instructions. The problem of testing instructions using the very instructions which may possibly be corrupt is addressed by developing a signature passed from instruction to instruction providing a low likelihood of a false positive outcome. A time-out system is used in the evaluation of the test calculation to capture a wide variety of other pathological operating conditions.

Abstract: A data protection method is provided that includes determining a compressibility score of one or more lines of data stored in a memory. The memory includes a first area characterized by a first reliability level and a second area characterized by a second reliability level. Lines of data with a first compressibility score are migrated to the first area of the memory. Lines of data with a second compressibility score are migrated to the second area of the memory.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: An apparatus and method for determining an abnormal ROM update in a portable terminal. The apparatus includes a ROM update unit for increasing a value of an update start counter when a ROM update process is performed, and increasing a value of an update finish counter when the ROM update process is finished. The ROM update unit loads the values of the update start counter and the update finish counter, and compares the values of the two counters to determine that the ROM update process has been normally performed before the portable terminal abnormally operates.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads, a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: Systems and methods for intelligently reducing the number of log-likelihood ratios (LLRs) stored in memory of a wireless communication device are described herein. In one aspect, the systems and methods described herein relate to selecting LLRs for storage based on a quality metric. In another aspect, the systems and methods described herein relate to improving communication quality in response to available memory capacity.

Abstract: A disk drive is disclosed comprising a head actuated over a disk comprising a plurality of data tracks. A read signal emanating from the head is sampled to generate read samples, and first log-likelihood ratios (LLRs) are generated in response to the read samples. The first LLRs are biased to generate biased LLRs, and the biased LLRs are decoded into a data sequence, wherein the biased LLRs increase an error rate of the data sequence.

Abstract: A system that automatically prompts a computer user about a known limitation of a product component, such as a software component. Generally, there is contemplated herein a method including providing a physical computing device, running software in the physical computing device, detecting whether the software has a known limitation, and automatically providing an advisory responsive to detecting a known software limitation.

Abstract: According to the presently disclosed subject matter there is provided inter alia, a method and system which enable to uncover errors which are correctible by a data integrity mechanism in a computer system. The same data is read with the help of two different types of read commands. The first command is a read command which does not implement an inherent ECC and therefore does not correct corrupted data. The second command is a read command which includes an ECC and is adapted to correct errors which are detected in the data which is being read. The data obtained by each of the two read commands is compared, and in cases where a difference is identified between the two data, it is determined that an error has been detected and corrected by the ECC.

Abstract: Methods and structure for diagnosing errors in the initialization of DDR memory “on board” a storage controller or a storage expander are presented herein. The features and aspects discussed herein allow for the debugging of the DDR memory initialization. A memory diagnostic system is operable on a storage controller and includes an initialization module in communication with a firmware module of the storage controller. The memory diagnostic system is adapted to initialize a Double Date Rate (DDR) memory of the storage controller. The memory diagnostic system also includes an application programming interface adapted to retrieve initialization information from the initialization module and transfer the initialization information to a debug system via a direct communication link between the application programming interface and the debug system to diagnose the initialization of the DDR memory and to debug the initialization module based on the initialization information.

Abstract: A supporting apparatus includes a configuration-information storage unit having stored therein dependencies among devices in association with a list of the devices. When information about a device where a failure has occurred is input, a dependency among devices including the faulty device is obtained from the configuration-information storage unit. Based on the obtained dependency among devices including the faulty device and information about the faulty device, learning data with the dependency and a cause of failure being associated with each other is created. Then, based on the created learning data, a solution procedure indicative of a procedure for specifying the cause of failure is generated by using, for example, algorithm ID3.

Abstract: Execution traces are collected from multiple execution instances that exhibit performance issues such as slow execution. Call stacks are extracted from the execution traces, and the call stacks are mined to identify frequently occurring function call patterns. The call patterns are then clustered, and used to identify groups of execution instances whose performance issues may be caused by common problematic program execution patterns.

Abstract: Provided is a storage apparatus for providing a logical storage area as a data storage area to an external apparatus, comprising: a physical storage medium for creating the logical storage area; first and second storage control modules each of which is communicatively coupled to the physical storage medium to control data input/output processing between the external apparatus and the logical storage area; and first and second power supply modules each of which supplies power to the physical storage medium and the first and second storage control modules and includes a blower for generating a cooling airflow to cool down the physical storage medium and the first and second storage control modules, wherein the blower of the first power supply module generates a first cooling airflow which flows through the physical storage medium, the first storage control module, and the first power supply module, the blower of the second power supply module generates a second cooling airflow which flows through the physical s

Abstract: A computing device monitors multiple hosts. A first host that does not have access to a data store is identified. A determination is made as to whether other hosts have access to the data store. When the other hosts do have access to the data store, it is determined that the first host is malfunctioning. A host error notification may then be sent to an administrator.

Abstract: A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in the FCDR, and merges the stored data with data-to-be-stored in the store data output from the execution unit and stored in the STBs or the WBs to generate new store data. The cache memory controlling unit then writes the generated new store data in the DATA-RAM, generates an ECC from the new store data, and writes the ECC in the ECC-RAM.

Abstract: An error correction circuit and method applicable to a DisplayPort receiver is disclosed. While decoding errors occur at a decoding stage, the invention actively adjusts settings of a physical layer by using an ANSI10B/8B decoder and performs data recovery by using a correcting unit that improves the reliability of input data.

Abstract: The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes a single R memory component including R banks, a Q memory component including Q banks, a channel detector memory component to store channel extrinsic information associated with current and previous codewords, and an iterative decoder communicatively coupled with the single R memory component, the Q memory component, and the channel detector memory component. The apparatus can be configured to alternate among the R banks for storing R data associated with a current codeword. The apparatus can be configured to alternate among the Q banks for storing Q data associated with a current codeword.

Abstract: A system, method, and computer program product replace a failed node storing data relating to a portion of a data file. An indication of a new storage node to replace the failed node is received at each of a plurality of available storage nodes. The available storage nodes each contain a plurality of shares generated from a data file. These shares may have been generated based on pieces of the data file using erasure coding techniques. A replacement share is generated at each of the plurality of available storage nodes. The replacement shares are generated by creating a linear combination of the shares at each node using random coefficients. The generated replacement shares are then sent from the plurality of storage nodes to the indicated new storage node. These replacement shares may later be used to reconstruct the data file.

Abstract: A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory.

Abstract: Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.