Abstract: A particularly simple and simultaneously fail-safe control system has a control computer for interchanging data with at least one peripheral, and at least one further control computer connected to the first-mentioned control computer via a communication channel. The further control computer is configured to assume at least part of the functionality of the control computer. The control computer is designed, in the event of partial failure thereof, to forward data received by the further control computer via the communication channel to the peripheral and/or to forward data received by the peripheral to the further control computer via the communication channel. There is also provided such a control computer and a method for operating a control system.

Abstract: A method of RAID migration comprising reading first and second blocks from a first RAID array. Said first blocks are written to a second RAID array within a first write cycle. Said second blocks are read simultaneously with a portion of said first write cycle in a pipelined fashion. In a first embodiment, pipelining increases the speed of RAID migration from a one-disk stripe array to a two-disk mirror array. In a second embodiment, pipelining and the use of duplicate blocks increases the speed of RAID migration from a two-disk mirror array to a three-disk RAID 5 array. In a third embodiment, pipelining and the use of duplicate blocks increases the speed of RAID migration from a three-disk RAID 5 array to a four-disk RAID 5 array.

Abstract: A system for decoding data includes a symbol based error correction code device. The error correction code device includes a channel detector configured to generate probability mass function (PMF) information. The error correction code device further includes a decoder coupled to the channel detector. The decoder is configured to use the PMF information from the channel detector to perform an error correction code operation. The decoder also is configured to generate PMF information. The channel detector is configured to receive extrinsic PMF information in a turbo equalization scheme.

Abstract: Error handling and recovery, implemented in a storage server, detects an error in a peripheral device of the storage server. If the error is recoverable, the system contains the error by isolating the peripheral device to prevent the generation of additional interrupt signals and migrates operations of the peripheral device to a back-up peripheral device. The system initiates error recovery by calling a recovery routine and a reinitialization routine, both provided by a device driver for the peripheral device. After device recovery is complete, the system migrates operations of the back-up peripheral device back to the peripheral device.

Abstract: A transmitting system, a receiving system, a method of processing broadcast signals and a method of receiving broadcast signals are disclosed.

Abstract: Methods, media, and systems for detecting an anomalous sequence of function calls are provided. The methods can include compressing a sequence of function calls made by the execution of a program using a compression model; and determining the presence of an anomalous sequence of function calls in the sequence of function calls based on the extent to which the sequence of function calls is compressed. The methods can further include executing at least one known program; observing at least one sequence of function calls made by the execution of the at least one known program; assigning each type of function call in the at least one sequence of function calls made by the at least one known program a unique identifier; and creating at least part of the compression model by recording at least one sequence of unique identifiers.

Abstract: This invention concerns packet recovery for real-time (live) multi-media communication over packet-switched networks like the Internet. Such communication includes video, audio, data or any combination thereof. The invention comprises forward error correction (FEC) algorithms addressing both random and burst packet loss and errors, and that can be adjusted to tradeoff the recoverability of missing packets and the latency incurred.

Abstract: A nonvolatile memory device comprises a memory cell array configured to store one or more bits per memory cell, a read and write circuit configured to access the memory cell array, a control logic component configured to control the read and write circuit to sequentially execute read operations of a selected memory cell at least twice to output a read data symbol, and an error correcting unit configured to correct an error in the read data symbol based on a pattern of the read data symbol to output an error-corrected symbol.

Abstract: A differential communication bus comprising a master module and a plurality of slave modules connected to at least first and second conductors whereby to communicate between the master and slave modules. The master module comprises a driver for applying first and second voltages respectively to the first and second conductors and for sourcing and sinking currents in the first and second conductors. The driver controls a difference between the first and second voltages and a common mode value of the first and second voltages. The driver includes first sourcing and sinking current limiters and second sourcing and sinking current limiters for limiting the currents in the first and second conductors. The master module is selectively responsive to a fault condition triggering simultaneous activation of the first and second sourcing current limiters or of the first and second sinking current limiters to disable the driver.

Abstract: Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.

Abstract: An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.

Abstract: A 1-bit error correction method is provided. In the method, a variable node at which an error has occurred is detected based on a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes and an error in a bit corresponding to the detected variable node is corrected.

Abstract: A method of handling packet loss uses error-correcting codes and block rearrangement. This method divides the original data stream into data blocks, then codes the blocks by error-correcting codes. After coding the blocks, rearranges the coding blocks for spreading original data into new blocks and then transmitting the new blocks. After receiving the transmitted blocks, reverse-rearrangs the received blocks and decode the blocks. Combine the decoded blocks into original data stream in the end.

Abstract: Hardware faults in data storage systems are diagnosed. User I/O errors are received. Disk drive port error counters, primary port error counters, and expansion port error counters are read. A user I/O error threshold is modified based on the error counter readings. Depending on the type of errors counted, the user I/O error threshold may be increased or decreased. Once a first quantity of user I/O errors exceeds the modified user I/O error threshold, a faulty component is identified.

Abstract: Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. Moreover, an error-detection circuit, which is coupled to the encoder circuit, generates and stores error-detection information associated with the set of M symbols, where the error-detection information facilitates subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. Additionally, a receiver circuit receives feedback information from the other circuit. This feedback information includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space.

Abstract: A method for detecting an improper removal of the electronic equipment. In the method, having received a command from a higher-level device, the electronic equipment (card reader) executes processing operations in accordance with the command. The electronic equipment includes a first RAM for saving electronic information including the confidential data, a detection means (such as a switching circuit) for detecting the improper removal of the electronic equipment, a power supply control IC for shutting off a power supply to the RAM in accordance with a signal coming from the detection means, and a second RAM being separate from and independent of the first RAM. Data saved in the RAM is not deleted even if the power supply is shut off by the power supply control IC. Then, the detection means is activated after the confidential data saved in the first RAM is copied to the second RAM.

Abstract: A cache device is disposed on a connection path between a user computer executing a software application and a network. The application exchanges data with a further computer via the network. The cache device includes a cache memory and a processor. The cache device is configured to measure, by the processor, a first latency between the user computer and the further computer. The cache device is further configured to determine an acceptable latency range based on the latency and a requirement of the software application. The cache device is further configured to measure a second latency between the user computer and the further computer. The cache device is further configured to store, in the cache memory, a set of data transmitted from the user computer to the further computer, if the second latency is not within the acceptable latency range.

Abstract: Embodiments of an apparatus and method for coding of wireless transmissions channel are generally described herein. Other embodiments may be described and claimed.

Abstract: An error correcting controller for connecting an old host controller having an old error correcting function with a new flash memory which requires a new error correcting function is provided. When the old host controller needs to write data into the new flash memory, the error correcting controller generates a new error correcting code according to the new error correcting function for the data. Then, when the old host controller needs to read the data from the new flash memory, the error correcting controller performs an error correcting procedure according to the new error correcting code and transmits information to the old host controller according to the result of the error correcting procedure and the old error correcting function. Accordingly, it is possible to allow the old host controller to access the new flash memory without changing the architecture of the old host controller.

Abstract: A method and apparatus to select bits for puncturing forward error correcting code frames to synthesize higher code rates. For example, there is provided a method of puncturing a digital data stream that includes a first parity bit stream and a second parity bit stream to generate a punctured bit stream. In one example, the method includes operating a first counting loop to select a first number of punctured bits from the first parity bit stream, comparing the first number of punctured bits with a desired number of bits for the punctured bit stream, and if the first number of punctured bits is less than the desired number of bits, operating a second counting loop to select a second number of punctured bits from the second parity bit stream until the sum of the first number of punctured bits and the second number of punctured bits is equal to the desired number of bits for the punctured bit stream.