Abstract: Technology is disclosed herein that the enhances the measurability and scalability of qubits in a quantum computing environment. In an implementation, a superconducting amplifier device comprises a parametric amplifier and a tunable coupling between the parametric amplifier and a readout cavity external to the superconducting amplifier device. The tunable coupling allows an entangled signal, associated with a qubit in the readout cavity, to transfer from the readout cavity to the parametric amplifier. The parametric amplifier amplifies the entangled signal to produce an amplified signal as output to a measurement sub-system.

Abstract: A method of determining overlay of a patterning process, the method including: obtaining a detected representation of radiation redirected by one or more physical instances of a unit cell, wherein the unit cell has geometric symmetry at a nominal value of overlay and wherein the detected representation of the radiation was obtained by illuminating a substrate with a radiation beam such that a beam spot on the substrate was filled with the one or more physical instances of the unit cell; and determining, from optical characteristic values from the detected radiation representation, a value of a first overlay for the unit cell separately from a second overlay for the unit cell that is also obtainable from the same optical characteristic values, wherein the first overlay is in a different direction than the second overlay or between a different combination of parts of the unit cell than the second overlay.

Abstract: For manufacturing-related reasons, the qubits of known quantum computers are not to be regarded as equivalent, but instead a standard quantum computer has not only high-performance qubits with long decoherence times and good fidelities of operation but also low-performance qubits with short decoherence times and poor fidelities of operation. The invention utilizes these by subdividing a system to be modeled with such a quantum computer into a bath part of low relevance and a cluster part of high relevance, wherein a rough description of the bath part is assigned to the low-performance qubits and an exact description of the cluster part is assigned to the high-performance qubits.

Abstract: A stencil-avoidance design method, a stencil-avoidance design device, an electronic device, and a non-transitory storage medium are provided. The method includes: obtaining a plurality of first regions and a plurality of first stencil aperture regions; determining whether a shortest distance between a selected first region of the plurality of first regions and a selected first stencil aperture region of the plurality of first stencil aperture regions is within a preset threshold range; further obtaining a second region and a second stencil aperture region if the shortest distance is within the preset threshold range, and then obtaining a third region; performing a collision step if a collision test is required, and obtaining a final stencil aperture region. The above method can improve the efficiency, accuracy, coverage, and comprehensiveness of the stencil avoidance design.

Abstract: Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. A plurality of training masks, for a machine learning (ML) model, are generated by synthesizing one or more polygons, relating to a design pattern for the semiconductor device, using Inverse Lithography Technology (ILT) (106). The ML model is trained using both the plurality of training masks generated using ILT, and the design pattern for the semiconductor device, as inputs (108). The trained ML model is configured to synthesize one or more masks, for use in manufacturing the semiconductor device, based on the design pattern (110).

Abstract: A system and method for using a programmable macro built-in self-test (BIST) to test an integrated circuit. The method includes receiving, by a built-in self-test (BIST) controller of an integrated circuit (IC) device from a testing equipment, a test vector of a first type for testing a first region of the IC device. The method includes identifying, based on the test vector of the first type, a first BIST engine of a plurality of BIST engines associated with the first region of the IC device. The method includes generating, based on the test vector of the first type, a first command of the second type. The method includes configuring, based on the first command of the second type, the first BIST engine of the plurality of BIST engines to cause the first BIST engine to perform a first set of tests on the first region of the IC device.

Abstract: A method for determining a correction for an apparatus used in a process of patterning substrates, the method including: obtaining a group structure associated with a processing history and/or similarity in fingerprint of to be processed substrates; obtaining metrology data associated with a plurality of groups within the group structure, wherein the metrology data is correlated between the groups; and determining the correction for a group out of the plurality of groups by applying a model to the metrology data, the model including at least a group-specific correction component and a common correction component.

Abstract: A method includes steps of dividing a first arrangement of metal lines in a circuit layout into two sets of metal lines, a first set of metal lines in a peripheral area, and a second set of metal lines in a center area. The arrangement of metal lines is configured to electrically connect to contacts of a second layer of the circuit layout. The method includes adjusting a metal line perimeter of at least one metal line in the center area to make a second arrangement of metal lines, where each adjusted metal line perimeter is separated from contacts in the second layer of the integrated circuit layout by at least a check distance.

Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

Abstract: Provided are a method of forming a mask, the method accurately and quickly restoring an image on the mask to the shape on the mask, and a mask manufacturing method using the method of forming the mask. The method of forming a mask includes obtaining first images by performing rasterization and image correction on shapes on the mask corresponding to first patterns on a wafer, obtaining second images by applying a transformation to the shapes on the mask, performing deep learning based on a transformation relationship between ones of the first images and ones of the second images corresponding to the first images, and forming a target shape on the mask corresponding to a target pattern on the wafer, based on the deep learning. The mask is manufactured based on the target shape on the mask.

Abstract: Extraction of capacitance values from a design of an electrical circuit can use a set of trained neural networks to generate extracted capacitance values from the circuit using a representation of the Green's function.

Abstract: A method of determining a parameter of a patterning process, the method including: obtaining a detected representation of radiation redirected by a structure having geometric symmetry at a nominal physical configuration, wherein the detected representation of the radiation was obtained by illuminating a substrate with a radiation beam such that a beam spot on the substrate was filled with the structure; and determining, by a hardware computer system, a value of the patterning process parameter based on optical characteristic values from an asymmetric optical characteristic distribution portion of the detected radiation representation with higher weight than another portion of the detected radiation representation, the asymmetric optical characteristic distribution arising from a different physical configuration of the structure than the nominal physical configuration.

Abstract: Embodiments of the disclosure provide a battery management system (BMS) including: a first controller monitoring a first battery cell array having at least one battery cell and configured to measure an operating parameter of the first battery cell array; and a second controller monitoring a second battery cell array having at least one battery cell and configured to measure an operating parameter of the second battery cell array, and communicatively coupled to the first controller. The first controller is selectable between: an active mode for receiving the measured operating parameter of the second battery cell array from the second controller, and detecting a fault in the first or the second battery cell array based upon the measured operating parameters thereof, and a passive mode for measuring the operating parameter of the first battery cell array, and transmitting the measured operating parameter to the second controller.

Abstract: An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of physical tiles in a reticle set. The physical tiles may include a center tile forming pixel circuitry on the image sensor die and peripheral tiles forming non-pixel circuitry on the image sensor die. Each of the physical tiles may be sized based on an integer multiple of a virtual unit tile. As such, the physical tiles may have dimensions that are not required to be an integer multiple of the smallest physical tile. The step and repeat exposure process may use the unit lengths of the virtual unit tile to properly position the die relative to the processing tools.

Abstract: A board design assistance device includes a design data acquirer to acquire design data for a printed circuit board, a first determiner to determine, based on the design data for the printed circuit board, whether a lengthwise direction of board fiber in the printed circuit board is perpendicular to a longitudinal direction of an electronic component mounted on the printed circuit board, a second determiner to determine, based on the design data for the printed circuit board, whether a wire is routed crosswise from a pad receiving the electronic component mounted on the printed circuit board, and a notifier to provide a notification including error information specifying an electronic component determined to have a longitudinal direction not perpendicular to the lengthwise direction of the board fiber and determined to be connected to a pad from which a wire is not routed crosswise.

Abstract: A method for characterizing post-processing data in terms of individual contributions from processing stations, the post-processing data relating to a manufacturing process for manufacturing integrated circuits on a plurality of substrates using a corresponding processing apparatus for each of a plurality of process steps, at least some of the processing apparatuses each including a plurality of the processing stations, and wherein the combination of processing stations used to process each substrate defines a process thread for the substrate; the method including: obtaining post-processing data associated with processing of the plurality of substrates in a cyclic sequence of processing threads; and determining an individual contribution of a particular processing station by comparing a subset of the post-processing data corresponding to substrates having shared process sub-threads, wherein a process sub-thread describes the process steps of each process thread other than the process step to which the particu

Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.

Abstract: A method of generating an integrated circuit includes providing a placing layout of the integrated circuit; generating a routed layout of the integrated circuit, the routed layout includes a layout region with a systematic design rule check (DRC) violation; generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in a plurality of placement recipes; extracting features of the placing layout to obtain an extracted data; extracting features of the layout region with the systematic DRC violation to obtain an extracted routing data; performing a training process upon the extracted data and the extracted routing data to generate a plurality of aggregated-cluster models; and selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models.

Abstract: A quantum computing service includes connections to multiple quantum hardware providers that are configured to execute quantum circuits using quantum computers based on different quantum technologies. The quantum computing service enables a customer to define a quantum algorithm/circuit in an intermediate representation and select from any of a plurality of supported quantum computing technologies to be used to execute the quantum algorithm/quantum circuit.

Abstract: A wireless charging method includes: acquiring a charging type supported by a wireless charging device after handshake communication with the wireless charging device; and selecting a first receiving assembly and/or a second receiving assembly to charge batteries of a foldable-screen electronic device based on the charging type. By arranging the first receiving assembly and the second receiving assembly on the foldable-screen electronic device, at least one of the receiving assemblies can be selected for wireless charging the batteries of the electronic device when one side surface of the foldable-screen electronic device is proximal to the wireless charging device, thereby improving charging efficiency and shortening charging time. User experience can be improved as the users do not need to select a specified side surface for charging.