Patents Examined by Nghia M. Doan
  • Patent number: 11687007
    Abstract: A method for categorizing a substrate subject to a semiconductor manufacturing process including multiple operations, the method including: obtaining values of functional indicators derived from data generated during one or more of the multiple operations on the substrate, the functional indicators characterizing at least one operation; applying a decision model including one or more threshold values to the values of the functional indicators to obtain one or more categorical indicators; and assigning a category to the substrate based on the one or more categorical indicators.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 27, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Arnaud Hubaux, Johan Franciscus Maria Beckers, Dylan John David Davies, Johan Gertrudis Cornelis Kunnen, Willem Richard Pongers, Ajinkya Ravindra Daware, Chung-Hsun Li, Georgios Tsirogiannis, Hendrik Cornelis Anton Borger, Frederik Eduard De Jong, Juan Manuel Gonzalez Huesca, Andriy Hlod, Maxim Pisarenco
  • Patent number: 11681845
    Abstract: Systems and techniques that facilitate quantum circuit valuation are provided. In various embodiments, a system can comprise an input component that can access a first quantum circuit. In various embodiments, the system can further comprise a valuation component that can appraise the first quantum circuit based on one or more factors (e.g., frequency factor, complexity factor, resource factor, similarity factor), thereby yielding a value score that characterizes the first quantum circuit. In various instances, the system can further comprise an execution component that can recommend deployment of the first quantum circuit based on determining that the value score exceeds a threshold.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: June 20, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Frederik Frank Flöther, Robert E. Loredo, Shikhar Kwatra, Paul R. Bastide
  • Patent number: 11675954
    Abstract: A method of designing a device includes identifying a pin to be inserted into a first layer of the device, wherein the first layer has a plurality of first routing tracks, and each of the plurality of first routing tracks extend in a first direction. The method further includes identifying a blocking shape on a second layer different from the first layer, wherein the second layer has a plurality of second routing tracks, and each of the plurality of second routing tracks extends in a second direction different from the first direction. The method further includes determining at least one candidate location for the pin in the first layer based on the plurality of first routing tracks of the first layer. The method further includes setting a location for the pin in the first layer based on the determined at least one candidate location.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Hsiung Chen, Jyun-Hao Chang, Ting-Wei Chiang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang
  • Patent number: 11669671
    Abstract: A semiconductor structure includes a power grid layer (including a first metallization layer) and a set of cells. The first metallization layer includes: conductive first and second portions which provide correspondingly a power-supply voltage and a reference voltage, and which have corresponding long axes oriented substantially parallel to a first direction; and conductive third and fourth portions which provide correspondingly the power-supply voltage and the reference voltage, and which have corresponding long axes oriented substantially parallel to a second direction substantially perpendicular to the first direction. The set of cells is located below the PG layer. Each cell is monostate cell which lacks an input signal and has a single output state. The cells are arranged to overlap at least one of the first and second portions in a repeating relationship with respect to at least one of the first or second portions of the first metallization layer.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang
  • Patent number: 11657196
    Abstract: A method includes detecting submission of a first quantum circuit for compilation, the first quantum circuit comprising a first set of quantum logic gates; generating a first gate index, the first gate index comprising an ordered table of a subset of the set of quantum logic gates, each quantum logic gate of the subset of quantum logic gates including a corresponding set of qubits acted on by the quantum logic gate; comparing the first gate index with a second gate index to determine a structural equality of the first quantum circuit and the second quantum circuit; and parameterizing, in response to determining a structural equality of the first quantum circuit and the second quantum circuit, a first set of parameters of a second set of quantum logic gates of the second quantum circuit with a second set of parameters of the first set of quantum logic gates.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 23, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Don Greenberg, Marco Pistoia, Ali Javadiabhari, Richard Chen, Jay M. Gambetta
  • Patent number: 11639657
    Abstract: A system includes equipment for at least one of formation of, stimulation of, or production from a wellbore, a processor, and a non-transitory memory device. The processor is communicatively coupled to the equipment. The non-transitory memory device contains instructions executable by the processor to cause the processor to perform operations comprising training a hybrid deep generative physics neural network (HDGPNN), iteratively computing a plurality of projected values for wellbore variables using the HDGPNN, comparing the projected values to measured values, adjusting the projected values using the HDGPNN until the projected values match the measured values within a convergence criteria to produce an output value for at least one controllable parameter, and controlling the equipment by applying the output value for the at least one controllable parameter.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: May 2, 2023
    Assignee: Landmark Graphics Corporation
    Inventor: Srinath Madasu
  • Patent number: 11636242
    Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: April 25, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashish Khandelwal, Sreenivasan K. Koduri, Nikhil Gupta, Timothy W. Fischer
  • Patent number: 11636372
    Abstract: Systems, computer-implemented methods, and computer program products that can facilitate determining a state of a qubit are described. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an output receiving component that can receive, in response to a request, output representative of a quantum state of a qubit of a quantum computing device, and a classifying component that classifies the quantum state of the qubit of the quantum computing device based on the output representative of the quantum state of the qubit. The system can further include a configuring component that can configure the classifying component based on a characteristic of the request.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 25, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ken Inoue, Maika Takita, Antonio Corcoles-Gonzalez, Scott Douglas Lekuch
  • Patent number: 11630703
    Abstract: A computing device is provided, including a cluster update accelerator circuit configured to receive signals encoding a combinatorial cost function of a plurality of variables and a connectivity graph for the combinatorial cost function. In an energy sum phase, the cluster update accelerator circuit may determine a respective plurality of accumulated energy change values for the combinatorial cost function based at least in part on the connectivity graph. In an update phase, the cluster update accelerator circuit may determine a respective update indicator bit for each accumulated energy change value. In an encoder phase, based on the plurality of update indicator bits, the cluster update accelerator circuit may select a largest update-indicated cluster of the variables included in the connectivity graph. The cluster update accelerator circuit may output an instruction to update the variables included in the largest update-indicated cluster.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 18, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Christopher Anand Pattison, Helmut Gottfried Katzgraber, Matthias Troyer
  • Patent number: 11620564
    Abstract: Method, apparatus and product for modeling of quantum circuits and usages thereof. A method comprises obtaining a model of a quantum circuit that comprises a set of decision variables, corresponding domains, and constraints, wherein the set of decision variables comprise gate assignment decision variables that define an assignment of a gate to a qubit in a cycle in the quantum circuit. The method comprises automatically determining a set of valuations for the set of decision variables. The set of valuations are selected from the corresponding domains and satisfy the constraints. Based on the set of valuations the quantum circuit is synthesized.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: April 4, 2023
    Assignee: CLASSIQ TECHNOLOGIES LTD.
    Inventors: Yehuda Naveh, Amir Naveh, Nir Minerbi, Ofek Kirzner, Adam Goldfeld, Shmuel Ur
  • Patent number: 11620548
    Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having an original schematic associated therewith and extracting one or more features for each net from the schematic. Embodiments may include storing one or more resistance or capacitance values for each net and applying the one or more resistance or capacitance values as labels for a machine learning model. Embodiments may also include training the machine learning model using one or more actual values to generate a trained model. Embodiments may further include receiving the trained model to predict parasitics for a stitching engine and generating a stitched schematic.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: April 4, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sai Bhushan, Elias Lee Fallon, Chirag Ahuja
  • Patent number: 11611237
    Abstract: A wireless power reception apparatus and a mobile terminal are provided. The wireless power reception apparatus includes the following. A coil includes a first end, a second end, and a tap. The coil defined by the first end and the second end is configured to provide a first voltage, and the coil defined by the first end and the tap is configured to provide a second voltage. A first rectifying unit coupled with the first end and the second end of the coil. A second rectifying unit coupled with the first end and the tap of the coil. A charging unit coupled with the first rectifying unit and configured to apply the first voltage to a battery for charging. A power supply unit coupled with the second rectifying unit and configured to apply the second voltage to power a wireless receiving chip.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: March 21, 2023
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Shebiao Chen, Jialiang Zhang
  • Patent number: 11604989
    Abstract: A system for ANN training through processing power of parked vehicles. The system can include a master computing device having a controller configured to control training of an ANN. The training can be performed at least partially in separate parts by computing devices of parked vehicles. The controller can be configured to separate computing tasks of training the ANN into separated tasks. Also, the controller can be configured to assign at least some of the separated tasks to selected computing devices of parked vehicles. The controller can also be configured to receive and assemble results of the separated tasks to train the ANN. The controller can also be configured to train the ANN according to the results. The master computing device can be configured to send the assigned tasks to the selected devices of the vehicles as well as receive, from the selected devices, the results of the assigned tasks.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Gil Golov, Robert Richard Noel Bielby
  • Patent number: 11604483
    Abstract: The present invention maintains the accuracy of a reference current used in a functional circuit. Disclosed is a current generator circuit including a functional circuit and a diagnostic circuit. The functional circuit uses a reference current. The diagnostic circuit diagnoses the reference current in accordance with a comparison result obtained from comparison between the period of a periodic signal generated based on the reference current and the period of a reference clock inputted from the outside.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 14, 2023
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Keishi Komoriyama, Minoru Migita, Yoichiro Kobayashi
  • Patent number: 11599690
    Abstract: A computing device includes a processor and a storage device. A wafer asset modeling module is stored in the storage device and is executed by the processor to configure the computing device to perform acts identifying and clustering a plurality of assets based on static properties of a wafer asset using a first module of the wafer asset modeling module. The clustered plurality of assets is determined based on dynamic properties of the wafer asset using a second module of the wafer asset modeling module. Event prediction is performed by converting a numeric data of the clustered plurality of assets to a natural language processing (NLP) domain by a third module of the wafer asset modeling module. One or more sequence-to-sequence methods are performed to predict a malfunction of a component of the wafer asset and/or an event based on past patterns. Prediction information is stored in the storage device.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 7, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elham Khabiri, Anuradha Bhamidipaty, Robert Jeffrey Baseman, Chandrasekhara K. Reddy, Srideepika Jayaraman
  • Patent number: 11586915
    Abstract: Collaborative filtering systems based on variational autoencoders (VAEs) are provided. VAEs may be trained on row-wise data without necessarily training a paired VAE on column-wise data (or vice-versa), and may optionally be trained via minibatches. The row-wise VAE models the output of the corresponding column-based VAE as a set of parameters and uses these parameters in decoding. In some implementations, a paired VAE is provided which receives column-wise data and models row-wise parameters; each of the paired VAEs may bind their learned column- or row-wise parameters to the output of the corresponding VAE. The paired VAEs may optionally be trained via minibatches. Unobserved data may be explicitly modelled. Methods for performing inference with such VAE-based collaborative filtering systems are also disclosed, as are example applications to search and anomaly detection.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: February 21, 2023
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: William G. Macready, Jason T. Rolfe
  • Patent number: 11571989
    Abstract: A module-based framework evaluates designs of advanced start stop systems, particularly 12 V advanced start stop systems. The framework separates vehicle and battery analysis and uses a power profile to evaluate different designs of the vehicles and batteries. Particularly, the framework can evaluate different battery solutions and compare performances as a function of drive cycles, motor size, and electrical loads. In addition to modeling, actual batteries are tested for the same power inputs for validating performance differences. This framework identifies performance limiting components for determination of the vehicle system component optimization.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 7, 2023
    Assignee: CPS Technology Holdings LLC
    Inventors: Zhenli Zhang, Zhihong Jin, Tom M. Watson
  • Patent number: 11569675
    Abstract: A charging device, a terminal, and a method for controlling charging are provided. The charging device includes a wireless receiving circuit, a charging interface, a charging management module, and a control module. The wireless receiving circuit is configured to convert a wireless charging signal received into charging electrical energy. The charging interface is configured to receive charging electrical energy supplied by an external power supply device. The charging management module is configured to adjust a voltage and/or current in the charging electrical energy output from the wireless receiving circuit or the charging interface. The control module is configured to control a first charging channel where the wireless receiving circuit and the charging management module are disposed to be switched on, and/or control a second charging channel where the charging interface and the charging management module are disposed to be switched on.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: January 31, 2023
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Shiming Wan
  • Patent number: 11556834
    Abstract: A device includes: a plurality of qubits arranged in a two-dimensional array and a plurality of readout resonators. Each readout resonator of a first readout resonator group is arranged to electromagnetically couple to a respective qubit of a first qubit group. Each readout resonator of a second readout resonator group is arranged to electromagnetically couple to a respective qubit of a second qubit group. A resonance frequency of each readout resonator of the first readout resonator group is within a first resonance frequency band, and a resonance frequency of each readout resonator of the second readout resonator group is within a second resonance frequency band that is different from the first resonance frequency band.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: January 17, 2023
    Assignee: Google LLC
    Inventors: Zijun Chen, Julian Shaw Kelly
  • Patent number: 11555854
    Abstract: A system for testing a circuit comprises scan chains, a controller configured to generate a bit-inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation. Here, the plurality of shift clock cycles for bit inverting occur every m shift clock cycles, and the child test pattern information comprises information of m and location of the plurality of shift clock cycles in the shift operation.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: January 17, 2023
    Assignee: Siemens Industry Software Inc.
    Inventors: Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer