Patents Examined by Patricia T. Nguyen
  • Patent number: 11595005
    Abstract: Envelope tracking systems for power amplifiers are provided herein. In certain embodiments, an envelope tracker is provided for a power amplifier that amplifies an RF signal. The envelope tracker includes a multi-level switching circuit having an output that provides an output current that changes in relation to an envelope signal indicating an envelope of the RF signal when the envelope tracker is operating in an envelope tracking mode. The multi-level switching circuit includes a multi-level supply (MLS) modulator that receives multiple regulated voltages of different voltage levels, and an MLS control circuit that controls the selection of the MLS modulator over time based on the envelope signal. When transitioning the MLS modulator from selection of one regulated voltage level to another regulated voltage level, the MLS control circuit provides a soft transition to gradually switch the regulated voltage levels.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: February 28, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Florinel G. Balteanu, Sabah Khesbak, Serge Francois Drogi, Shayan Farahvash, David Richard Pehlke
  • Patent number: 11588458
    Abstract: An amplifier circuit for a millimeter wave (mmW) communication system includes an amplifier coupled to a matching network, and a variable gain control circuit in the matching network, the variable gain control circuit having an adjustable gain control resistance, the adjustable gain control resistance having adjustable segments and a center node therebetween, the center node coupled to an alternating current (AC) ground.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 21, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Marco Vigilante, Chinmaya Mishra
  • Patent number: 11588454
    Abstract: Various embodiments are directed to apparatuses and methods to generate a first signal representing modulation data and a second signal representing an amplitude of the modulation data, the first signal and the second signal to depend on an output signal and vary a power supply voltage to a gain stage in proportion to the amplitude of the modulation data.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: February 21, 2023
    Assignee: Intel Corporation
    Inventors: Nicholas P. Cowley, Isaac Ali, William L. Barber
  • Patent number: 11581855
    Abstract: Disclosed is power amplifier circuitry having a bipolar junction power transistor with a base, a collector, and an emitter. The power amplifier circuitry includes bias correction sub-circuitry configured to generate a compensation current substantially opposite in phase and substantially equal in magnitude to an error current passed by a parasitic base-collector capacitance inherently coupled between the base and collector, wherein the bias correction sub-circuitry has a compensation output coupled to the base and through which the compensation current flows to substantially cancel the error current.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 14, 2023
    Assignee: Qorvo US, Inc.
    Inventor: Terry J. Stockert
  • Patent number: 11581644
    Abstract: An apparatus is disclosed for bidirectional amplification with phase-shifting. In example implementations, an apparatus includes a phase shifter with a bidirectional amplifier. The bidirectional amplifier includes a first transistor coupled between a first plus node and a second minus node, a second transistor coupled between a first minus node and a second plus node, a third transistor coupled between the first plus node and the second minus node, and a fourth transistor coupled between the first minus node and the second plus node. The bidirectional amplifier also includes a fifth transistor coupled between the first plus node and the second plus node, a sixth transistor coupled between the first minus node and the second minus node, a seventh transistor coupled between the first plus node and the second plus node, and an eighth transistor coupled between the first minus node and the second minus node.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: February 14, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Xinmin Yu, Lai Kan Leung
  • Patent number: 11575349
    Abstract: In some embodiments, radio-frequency amplifiers can include a plurality of narrow band power amplifiers implemented. Each narrow band power amplifier can be configured to operate with a high voltage in an average power tracking mode and be capable of being coupled to an output filter associated with a respective individual frequency band. Each narrow band power amplifier can be sized smaller than a wide band power amplifier configured to operate with more than one of the frequency bands associated with the plurality of narrow band power amplifiers.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 7, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventor: Philip John Lehtola
  • Patent number: 11575355
    Abstract: A multi-stage transimpedance amplifier (TIA) with an adjustable input linear range is disclosed. The TIA includes a first stage, configured to convert a single-ended current signal from an optical sensor of a receiver signal chain to a single-ended voltage signal, and a second stage, configured to convert the single-ended voltage signal provided by the first stage to a differential signal. In such a TIA, the input linear range may be adjusted using a clamp that is programmable with an output offset current to keep the second stage of the TIA from overloading and to maintain a linear transfer function without compression.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: February 7, 2023
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Joseph Adut, Jeremy Wong, Eugene L. Cheung, Brian D. Hamilton, Gregory A. Fung
  • Patent number: 11558014
    Abstract: A power amplifier circuit includes a first transistor having an emitter electrically connected to a common potential, a base to which a first high-frequency signal is input, and a collector from which a third high-frequency signal is output; a second transistor having an emitter electrically connected to the common potential, a base to which a second high-frequency signal is input, and a collector from which a fourth high-frequency signal is output; a first capacitance circuit electrically connected between the collector of the second transistor and the base of the first transistor; and a second capacitance circuit electrically connected between the collector of the first transistor and the base of the second transistor.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: January 17, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Satoshi Arayashiki, Satoshi Goto, Yusuke Tanaka
  • Patent number: 11555738
    Abstract: Systems and methods are disclosed for controlling nonequilibrium electron transport process and generating phonons in low dimensional materials. The systems can include a conductive sheet sandwiched between a first insulation layer and a second insulation layer; a first electrode conductively coupled to a first end of the conductive sheet; a second electrode conductively coupled to a second end of the conductive sheet; and a current source conductively coupled to the first electrode and the second electrode and configured to pass a current from the first electrode through the conductive sheet to the second electrode such that current generates a drift velocity of electrons in the conductive sheet that is greater than the speed of sound to generate phonons.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 17, 2023
    Assignee: President and Fellows of Harvard College
    Inventors: Mikhail D. Lukin, Trond Ikdahl Andersen, Bo Loren Dwyer, Javier Daniel Sanchez, Kartiek Agarwal
  • Patent number: 11552605
    Abstract: A digitally controlled grounded capacitor multiplier includes: a single capacitor directly connected at one end to an input voltage and at another end to a negative input of an operational amplifier; the operational amplifier including a negative feedback loop; and a digitally controlled current amplifier (DCCA) connected to an output of the operational amplifier. The DCCA digitally controls the digitally controlled grounded capacitor multiplier. The digitally controlled grounded capacitor multiplier comprises only two active devices consisting of the operational amplifier and the DCCA.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: January 10, 2023
    Assignees: SAUDI ARABIAN OIL COMPANY, KING FAHD UNIVERSITY OF PETROLEUM & MINERALS
    Inventors: Abdulrahman Alshuhail, Hussain Alzaher, Alaa El-Din Hussein
  • Patent number: 11552601
    Abstract: A power amplifier circuit includes an input-stage power amplifier configured to receive a radio-frequency input signal, an output-stage power amplifier configured to output an amplified radio-frequency output signal, and an intermediate-stage power amplifier disposed between the input-stage power amplifier and the output-stage power amplifier. The intermediate-stage power amplifier includes a first transistor, a second transistor, and a capacitor having a first end connected to an emitter of the first transistor and a second end connected to a collector of the second transistor. The intermediate-stage power amplifier receives a signal at a base of the second transistor thereof and outputs an amplified signal from a collector of the first transistor thereof.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: January 10, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shingo Yanagihara, Satoshi Tanaka
  • Patent number: 11539332
    Abstract: An amplification circuit includes a switch circuit, an amplifier, and a control circuit. The switch circuit has a first terminal coupled to a radio frequency signal input terminal or a system voltage terminal, a second terminal coupled to an input terminal of the amplifier, and a control terminal configured to receive a control signal. The amplifier amplifies a radio frequency signal. The control circuit generates the control signal according to a driving current generated by the amplifier. When the control circuit determines that the amplifier operates in a high power mode, the control circuit controls the control signal to adjust a conducting level between the first terminal and the second terminal of the switch circuit according to the intensity of the driving current.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: December 27, 2022
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Tien-Yun Peng
  • Patent number: 11533028
    Abstract: A radio frequency power amplifier with harmonic control circuit as well as method for manufacturing the same are disclosed. According to an embodiment, a radio frequency power amplifier includes: a planar dielectric substrate, a first conductive layer and a second conducting layer. The first conductive layer is disposed on a first side of the planar dielectric substrate. The second conducting layer is disposed on a second side of the planar dielectric substrate. The first conductive layer has a pattern comprising one or more harmonic control circuits. The second conductive layer acts as a ground plane. The second side of the planar dielectric substrate is opposite to the first side of the planar dielectric substrate.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: December 20, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Zhancang Wang, Chen He
  • Patent number: 11527998
    Abstract: An apparatus for turning off a cascode amplifier having a common-base transistor and a common-emitter transistor is disclosed that includes the cascode amplifier, a feedback circuit, and a bias circuit. The feedback circuit is configured to receive a collector-voltage from the collector of the common-emitter transistor when the common-emitter transistor is switched to a first OFF state and produce a first feedback signal. The collector-voltage is equal to an emitter voltage of the common-base transistor and the collector-voltage increases in response to switching the common-emitter transistor to the first OFF state. The bias circuit is configured to receive the first feedback signal and produce a bias-voltage. A first base-voltage is produced from the bias-voltage. The cascode amplifier is configured to receive the first base-voltage and a second base-voltage. The common-base transistor is configured to switch to a second OFF state in response to receiving the second base-voltage.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: December 13, 2022
    Assignee: Silanna Asia Pte Ltd
    Inventor: Stuart Ide Hodge, Jr.
  • Patent number: 11522497
    Abstract: An amplifier includes a package that includes a carrier amplifier having a carrier amplifier input and output, a peaking amplifier having a peaking amplifier input and output, and corresponding input and output leads. The package includes a first integrated passive device including a first capacitor structure. The first integrated passive device includes a first contact pad coupled to the peaking amplifier output and a second contact pad coupled to the peaking output lead. The package includes a second integrated passive device including a second capacitor structure. The second integrated passive device includes a third contact pad coupled to the carrier amplifier output and a fourth contact pad coupled to the carrier output lead. The amplifier includes input circuitry a combining node configured to combine a carrier output signal and a peaking output signal.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: December 6, 2022
    Assignee: NXP USA, Inc.
    Inventors: Ramanujam Srinidhi Embar, Jeffrey Spencer Roberts
  • Patent number: 11522505
    Abstract: A semiconductor integrated circuit includes an equalizer circuit configured to amplify a signal component in a particular frequency band of an input signal on a signal path after a coupling capacitor, a sampler circuit configured to convert a first signal outputted from the equalizer circuit to a digital signal, a detector circuit configured to output a second signal based on a frequency of appearance of two values included in the digital signal, and a compensator circuit configured to compensate for a shift of a DC voltage level on the signal path after the coupling capacitor based on the second signal outputted from the detector circuit.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: December 6, 2022
    Assignee: Kioxia Corporation
    Inventor: Yutaka Nakamura
  • Patent number: 11522498
    Abstract: Aspects of the subject disclosure may include a Doherty amplifier that includes a carrier amplifier having an output terminal, an output network coupled to the output terminal, and a peaking amplifier, wherein the output network comprises a non-linear reactance component, and wherein the non-linear reactance component changes an effective impedance of a load presented to the carrier amplifier when the peaking amplifier is off. Other embodiments are disclosed.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: December 6, 2022
    Assignee: NXP USA, Inc.
    Inventors: Joseph Staudinger, Matthew Russell Greene, Edward Provo Wallis Horne, Johannes Lambertus Holt, Peter Zahariev Rashev
  • Patent number: 11519754
    Abstract: Isolated circuit systems are provided. The systems include a primary side circuit and a secondary circuit, electrically isolated from each other. The primary side and secondary side circuits each utilize a direct current (DC) reference signal. The primary side circuit may use the DC reference signal in a modulation operation. The secondary side circuit may use the DC reference signal in a demodulation operation. The DC reference signal may be sent from the primary side circuit to the secondary side circuit, or from the secondary side circuit to the primary side circuit.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: December 6, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Wenhui Qin, Shaoyu Ma, Tianting Zhao, Fang Liu
  • Patent number: 11515846
    Abstract: An in-band extraction unit is configured to extract an in-band from an output signal. An out-band extraction unit is configured to extract at least one pair of out-bands including a low frequency side out-band and a high frequency side out-band from the output signal. An ADC is configured to convert the extracted in-band and out-bands to digital signals. A signal processing unit is configured to process information included in the digital signals converted by the analog to digital converter and adjust an operation of predistorting an input baseband digital signal to generate the output signal.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 29, 2022
    Assignee: NEC CORPORATION
    Inventors: Soubhik Deb, Masaaki Tanio
  • Patent number: 11515847
    Abstract: A packaged RF amplifier device includes input and output leads and a transistor die. The transistor die includes a transistor with a drain-source capacitance below 0.1 picofarads per watt. The device also includes a conductive connection between the transistor output terminal and the output lead, and a baseband termination circuit between the transistor output terminal and a ground reference node. The baseband termination circuit presents a low impedance to signal energy at envelope frequencies and a high impedance to signal energy at RF frequencies. The baseband termination circuit includes an inductive element, a resistor, and a capacitor connected in series between the transistor output terminal and the ground reference node. Except for a minimal impedance transformation associated with the conductive connection, the device is unmatched between the transistor output terminal and the output lead by being devoid of impedance matching circuitry between the transistor output terminal and the output lead.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: November 29, 2022
    Assignee: NXP USA, Inc.
    Inventors: Damon G. Holmes, Ning Zhu, Jeffrey Spencer Roberts, Jeffrey Kevin Jones