Abstract: An apparatus configured to reduce an offset of a Hall sensor includes a voltage-current conversion circuit and a current mirror circuit. The voltage-current conversion circuit is configured to generate a current configured to decrease when a voltage of an input terminal to which a bias current of a Hall sensor is input increases and increase when the voltage of the input terminal decreases. The current mirror circuit has a current mirror structure configured to feedback the bias current based on the current generated by the voltage-current conversion circuit.

Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

Abstract: System and method for integrating an input signal to generate an output signal. The system includes a first integrator configured to receive the input signal and generate an integrated signal based on at least information associated with the input signal, a second integrator configured to receive the integrated signal and generate the output signal based on at least information associated with the integrated signal, and a compensation capacitor coupled to the first integrator and the second integrator. The first integrator includes a first integration capacitor and a first operational amplifier including a first input terminal and a first output terminal, the first integration capacitor being coupled between the first input terminal and the first output terminal. The second integrator includes a second integration capacitor and a second operational amplifier including a second input terminal and a second output terminal.

Abstract: An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.

Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

Abstract: An impedance matching circuit is provided. The impedance matching circuit includes a reference voltage generator configured to generate a reference voltage. A code generator is configured to generate a first calibration code by comparing the reference voltage with a first voltage associated with a first node and a second calibration code by comparing the reference voltage with a second voltage associated with a second node. A first resistance unit is configured to supply the first voltage to the first node in response to the first calibration code to calibrate its resistance to be equal to a reference resistance. A second resistance unit is configured to supply the second voltage to the second node in response to the second calibration code to thereby calibrate its resistance to the reference resistance.

Abstract: A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.

Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.

Abstract: An example includes a circuit including a first AND gate including a first input terminal, a second input terminal, and an output terminal, a second AND gate including a first input terminal, a second input terminal, and an output terminal, and a third AND gate including a first input terminal, a second input terminal, and an output terminal. The circuit also includes an OR gate including a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, a third input terminal coupled to the output terminal of the third AND gate, and an output terminal.

Abstract: A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (I/O) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.

Abstract: A radio frequency switch device includes a first transistor and a second transistor; a compensation network coupled between a body terminal of the first transistor and a source/drain terminal of the second transistor; and a bootstrapping network having a first terminal coupled to a first bias terminal, a second terminal coupled to a gate terminal of the first transistor, and a third terminal coupled to the body terminal of the first transistor, wherein the bootstrapping network establishes a low impedance path between the gate terminal and the body terminal of the first transistor in response to a first voltage value of the first bias terminal, and wherein the bootstrapping network establishes a high impedance path between the gate terminal and the body terminal of the first transistor in response to a second voltage value of the first bias terminal.

Abstract: A step-up power-converter has stack nodes, each of which connects to a stack switch and to a pump capacitor to form a switched-capacitor network. Among the stack nodes are first and second stack-nodes. The second stack-node drives a particular stack switch from the plurality of stack switches. When all of the stack switches are open, the first voltage causes the first stack-node to have a first stack-node voltage and causes the second stack-node to have a second stack-node voltage that is less than the first stack-node voltage. During the first state, the second stack-node voltage is insufficient to drive the particular stack-switch. During the second state, the second stack-node voltage is sufficient to drive the particular stack-switch. Causing the switched-capacitor network to transition from the first state to the second state includes, among other things, causing the second stack-node voltage to become sufficient to drive the particular stack-switch.

Abstract: A filter device having desired characteristics is easily designed. The filter device includes a post-wall waveguide functioning as a resonator group including five congruent resonators (R1 to R5). The resonators (R1, R2) include therein respective control posts (CP1, CP2), and a shortest distance (di) from the control post (CPi) to a narrow wall of the resonator (Ri) satisfies d1>d2. The resonators (R4, R5) include therein respective control posts (CP4, CP5), and a shortest distance (dj) from the control post (CPj) to a narrow wall of the resonator (Rj) satisfies d4<d5.

Abstract: A switching transformer includes a primary circuit and a secondary circuit. The primary circuit includes a first input/output (I/O) terminal, a plurality of primary windings, and primary switching circuitry including at least one switch configured to selectively connect the plurality of primary windings in series or in parallel. The secondary circuit includes a second I/O terminal, a plurality of secondary windings, and secondary switching circuitry including at least one switch configured to selectively connect the plurality of secondary windings in series or in parallel.

Abstract: An ultrasound system includes a transmit-receive switch. The transmit-receive switch includes a combined transmit-receive and return-to-zero (RTZ) path. The combined transmit-receive and RTZ path includes a transistor with a first current terminal, a second current terminal, and a control terminal. The second current terminal of the transistor is coupled to a ground node via a first switch and is coupled to a receive node via a second switch. The ultrasound system also includes a receiver front-end circuit coupled to the receive node.

Abstract: A balun includes a first winding which has a first terminal coupled to an input, and a second terminal coupled to a reference potential terminal. The balun includes a second winding magnetically coupled to the first winding. The second winding has a first terminal coupled to a first differential output, a second terminal coupled to a second differential output, and a tap coupled to the reference potential terminal. The balun includes a first capacitor which has a first terminal coupled to the first winding and a second terminal coupled to the second winding. The balun includes a third winding which has a first terminal coupled to the reference potential terminal and a floating second terminal. The balun includes a second capacitor which has a first terminal coupled to the third winding and a second terminal coupled to the second winding.

Abstract: A switching method, including: electrically coupling a switching circuit to a first impedance circuit, a second impedance circuit, a positive terminal of a frequency generation circuit and a negative terminal of the frequency generation circuit; adjusting an impedance value of the second impedance circuit according to a first clock signal and a second clock signal outputted by the frequency generation circuit; periodically conducting the negative terminal to one of the first impedance circuit and the second impedance circuit by a first switching unit of the switching circuit; and periodically conducting the positive terminal to the other one of the first impedance circuit and the second impedance circuit by a second switching unit of the switching circuit.

Abstract: A smart antenna switching method is disclosed. Multiple wireless signal parameters of a wireless network environment are collected. Under a current operating phase, when a holding period of a to-be-switched antenna is 0, the qualities of wireless signals between an initial antenna and the to-be-switched antenna are compared according to the wireless signal parameters. When a comparing period of the to-be-switched antenna is 0, it is determined whether an antenna switching operation is performed. If the antenna switching operation is not performed, the next operating phase is served as the current operating phase. If the antenna switching operation is performed, a signal receiving-and-sending operating is switched from the to-be-switched antenna to the outdoor antenna or from the outdoor antenna to the to-be-switched antenna, and the previous operating phase is served as the current operating phase.

Abstract: An electronic device may include wireless circuitry. The wireless circuitry may include a quadratic phase generator for outputting a perfectly interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator may include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator may receive as inputs a chirp count and a word length. The switch may be configured to switchably feed one of two input values that are a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator may output full-bandwidth chirps or reduced-bandwidth chirps. Bandwidth reduction can be achieved by scaling the two input values of the switches.

Abstract: A signal transmitter includes a plurality of driver slices. Each of the driver slices includes a driving circuit, a plurality of first transistors, and a plurality of second transistors. The driving circuit receives an input signal and outputting an output signal. The first transistors provide a first impedance according to signals on gate terminals of the first transistors. The second transistors provide a second impedance according to signals on gate terminals of the second transistors. Each of the gate terminals of the first transistors and the second transistors is selectively coupled to a bias voltage which controls the corresponding first transistor or second transistor to operate in a triode region, or coupled to a predetermined voltage which controls the corresponding first transistor or second transistor to behave as a switch.