Abstract: An apparatus for performing baseline wander correction (BLWC) with the aid of differential wander current sensing includes filters and a correction circuit. The filters are positioned in a front-end circuit of a receiver and coupled to a set of input terminals of the receiver, and filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals, for further usage by the receiver. The correction circuit is positioned in the frontend circuit and electrically connected to the set of input terminals and the set of secondary terminals, and performs BLWC on the set of differential signals according to the set of input signals. In the correction circuit, amplifiers and resistors form a differential wander current sensor to sense differential wander current, and a set of current mirrors generate corresponding baseline wander compensation current to perform BLWC.

Abstract: A switch circuit includes first and second transistor stacks coupled in parallel between first and second ports. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variably-conductive path between the first and second ports. Each transistor of the first plurality of transistors has a gate terminal coupled to a first control terminal. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variably-conductive path between the first and second ports. Each transistor of the second plurality of transistors has a gate terminal coupled to a second control terminal. When implemented in a transceiver, first and second drivers are configured to simultaneously configure the first and second variably-conductive paths in a low-impedance state.

Abstract: A frequency locked loop circuit, including a frequency generation circuit, a first impedance circuit, a second impedance circuit and a switching circuit. The frequency generation circuit includes a positive terminal and a negative terminal. The frequency generation circuit outputs an output clock signal according to a voltage difference between the positive terminal and the negative terminal. The first impedance circuit and the second impedance circuit are electrically coupled to a first impedance node and a second impedance node, respectively. The second impedance circuit adjusts an impedance value of the second impedance circuit according to the output clock signal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node.

Abstract: A phase locked loop arrangement (1) beamforming comprises two or more phase locked loops. The loops include a phase comparator (21, 22) and an adjustable charge pump arrangement (31, 32) having a loop filter (51, 52) and charge pump current source (41, 42) with an adjustment input (?adj) connected to the loop filter (51, 52) to inject an adjustable charge pump current into the loop filter. A constant current source (71, 72) is configured to inject a first predetermined charge current into the loop filter (51, 52). The adjustable charge pump arrangements (31, 32) are connected to the respective phase comparators (21, 22) to provide a voltage control signal (vctrl) to an oscillator (61, 62) of the respective phase adjustable phase locked loop (11, 12) in response to the respective control signal (up, down) and to generate a phase deviation between the first and one of the at least one second oscillator signals (fosc1, fosc2) based on an adjustment signal applied to the adjustment input (?adj).

Abstract: In a test system that provides a high fidelity output signal, a transition driving circuit can selectively enable multiple, parallel current paths based on a desired voltage transition. The transition driving circuit can include a first switch configured to switch a first current path between an output node and a first current source/sink, and a second switch configured to switch a second current path between the output node and the first current source/sink. The transition driving circuit can include a control circuit that is configured to receive information about a desired voltage transition and, depending on a magnitude of the desired voltage transition, to selectively turn on one or both of the first and second switches to enable one or both of the first and second current paths to provide respective portions of the output signal from the first current source/sink to the output node of the test system.

Abstract: Systems and methods are disclosed for low-swing Schmitt triggers. For example, an apparatus includes a Schmitt trigger including an input node, an output node, and a feedback node that is configured to bear a feedback voltage level that is a sum of an input voltage level at the input node and an attenuated voltage level of the output node; a current source connected to the output node; a voltage sensor connected to the feedback node and configured to cause the current source to pull up an output voltage level at the output node responsive to the feedback voltage level crossing a threshold.

Abstract: Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.

Abstract: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Abstract: A semiconductor device includes a power semiconductor chip, a threshold setting unit and a breaker circuit. The power semiconductor chip is connected between an output terminal and an earth terminal, and is configured to be turned on or off according to a potential at a gate terminal thereof. The threshold setting unit outputs an interrupt signal upon detecting that a voltage of a control signal received at an input terminal is lower than a predetermined voltage. The breaker circuit is connected between the gate terminal and the earth terminal, and switches on upon receiving the interrupt signal to thereby turn off the power semiconductor chip. The threshold setting unit includes a feed circuit that is configured to supply an electric charge stored in gate capacitance of the power semiconductor chip to the threshold setting unit responsive to a sudden drop of the voltage of the control signal.

Abstract: A circuit arrangement has an even number of semiconductor switches, which are connected in series and contain in each case two load terminals and a control terminal and are associated with one another in pairs. The circuit arrangement also contains, for each semiconductor switch, a driver for actuating the semiconductor switch via the control terminal thereof and, for every two semiconductor switches that form a switch pair, contains a switching power supply which is supplied with energy from an electrical voltage between the two load terminals of a first semiconductor switch of the switch pair and supplies both the driver of the first semiconductor switch and the driver of the second semiconductor switch of the switch pair with energy.

Abstract: Apparatus and associated methods relate to generating a programmable differential threshold with a common mode signal derived from a received signal, and comparing a differential component of the received signal to the programmable differential threshold signal to improve signal loss detection accuracy in the presence of noise. In an illustrative example, the comparison may be performed in a signal loss detection circuit. The signal loss detection circuit may, for example, process a received input signal in an independent path in parallel with a main signal path. The programmable differential threshold may be set to a predetermined level as a function of an acceptable noise level. Based on the comparison, some implementations may advantageously respond to received signal loss, which may result from, for example, a signal path interruption.

Abstract: A gate drive circuit includes: a drive unit configured to drive a gate of a main circuit element including a majority carrier device; and a drive capability change unit configured to cause the drive unit to increase a drive capability of turning on the main circuit element as a main circuit current that flows through the main circuit element decreases.

Abstract: The transition to a horizontal integrated circuit (IC) design flow has raised concerns regarding the security and protection of IC intellectual property (IP). Obfuscation of an IC has been explored as a potential methodology to protect IP in both the digital and analog domains in isolation. However, novel methods are required for analog mixed-signal circuits that both enhance the current disjoint implementations of analog and digital security measures and prevent an independent adversarial attack of each domain. A methodology generates functional and behavioral dependencies between the analog and digital domains that results in an increase in the adversarial key search space. The dependencies between the analog and digital keys result in a 3× increase in the number of iterations required to complete the SAT attack.

Abstract: A drive circuit includes: a current capability switch configured to switch a current capability of driving an output transistor of a switching power supply according to whether a switch current flowing through the output transistor is in a continuous mode or in a discontinuous mode.

Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. A current mirror arrangement sources a first current to the second node and sinks a second current from a third node. A comparator causes the control signal to direct the charge pump circuit to generate the charge pump output signal as having a voltage that ramps upwardly in magnitude (but negative in sign) if the voltage at the second node is greater than the voltage at the third node, and causes the control signal to direct the charge pump circuit to cease the ramping of the voltage of the charge pump output signal if the voltage at the second node is at least equal to the voltage at the third node.

Abstract: A semiconductor device includes a plurality of first transistor cells and a plurality of second transistor cells that are electrically connected in parallel between a collector electrode and an emitter electrode. A gate voltage on each of the plurality of first transistor cells is controlled by a first gate interconnection. A gate voltage on each of the plurality of second transistor cells is controlled by a second gate interconnection. A drive circuit is configured to: apply an ON-voltage of the semiconductor device to each of the first and second gate interconnections when the semiconductor device is turned on; and after a lapse of a predetermined time period since start of application of the ON-voltage, apply an OFF-voltage of the semiconductor device to the second gate interconnection and apply an ON-voltage to the first gate interconnection.

Abstract: A semiconductor device connectable between a first power-supply line connected to a power source and through which power is continuously supplied to a first circuit, and a second power-supply line that is not directly connected to the power source and is connected to a second circuit, includes a first switch connectable between the first and second power-supply lines and turned on in response to a signal for supplying power to the second circuit, a second switch connectable between the first and second power-supply lines and having a current supply capability higher than the first switch, and a control circuit configured to turn on the second switch when the first switch is turned on and a voltage applied to the second power-supply line has reached a threshold.

Abstract: A signal receiver circuit includes a first amplification circuit and an offset compensation circuit. The first amplification circuit generates a first amplified signal and a second amplified signal by amplifying an input signal and a reference voltage. The offset compensation circuit adjusts voltage levels of the first and second amplified signals based on a DC level of the input signal and a voltage level of the reference voltage.

Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

Abstract: Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values.