Patents Examined by Peter M Albrecht
  • Patent number: 11967620
    Abstract: Embodiments of the present disclosure provide a thin film transistor, a method of manufacturing the same, and a display device. The thin film transistor includes a metal conductive pattern layer, an interlayer insulating layer, and a metal oxide layer; and the metal conductive pattern layer includes: a light shielding pattern, a source signal line, and/or a drain signal line; the metal oxide layer includes: a source electrode, a drain electrode, and an active layer. An orthographic projection of the active layer on the base substrate has an overlapping region with that of the light shielding pattern; the source electrode extends through the interlayer insulating layer to connect to the source signal line, and/or the drain electrode extends through the interlayer insulating layer to connect to the drain signal line.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 23, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Pan Xu, Yicheng Lin, Cuili Gai, Ling Wang, Yongqian Li
  • Patent number: 11961865
    Abstract: A semiconductor device of the present disclosure includes: a semiconductor element disposed on a first surface side of a semiconductor substrate; a through-electrode that is provided through the semiconductor substrate in a thickness direction of the semiconductor substrate and introduces charge obtained in the semiconductor element to a second surface side of the semiconductor substrate; and an amplifier transistor that outputs an electrical signal based on the charge introduced by the through-electrode, the amplifier transistor using the through-electrode as a gate electrode and including a source region and a drain region around the through-electrode.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: April 16, 2024
    Assignee: Sony Group Corporation
    Inventors: Hideaki Togashi, Kosuke Nakanishi
  • Patent number: 11944020
    Abstract: A two-terminal resistive switching device (TTRSD) such as a non-volatile two-terminal memory device or a volatile two-terminal selector device can be formed according to a manufacturing process. The process can include forming an etch stop layer that is made of aluminum and can include forming a buffer layer below the etch stop layer and/or between the etch stop layer and a top electrode of the TTRSD.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: March 26, 2024
    Assignee: CROSSBAR, INC.
    Inventors: Sundar Narayanan, Natividad Vasquez, Zhen Gu, Yunyu Wang
  • Patent number: 11942456
    Abstract: A method of fabricating a multi-color display includes dispensing a photo-curable fluid over a display having an array of light emitting diodes (micro-LEDs) disposed below a cover layer. The cover has an outer surface with a plurality of recesses, and the photo-curable fluid fills the recesses. The photo-curable fluid includes a color conversion agent. A plurality of LEDs in the array are activated to illuminate and cure the photo-curable fluid to form a color conversion layer in the recesses over the activated LEDs. This layer will convert light from these LEDs to light of a first color. An uncured remainder of the photo-curable fluid is removed. Then the process is repeated with a different photo-curable fluid having a different color conversion agent and a different plurality of LEDs. This forms a second color conversion layer in different plurality of recesses to convert light from these LEDs to light of a second color.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Daihua Zhang, Yingdong Luo, Mingwei Zhu, Hou T. Ng, Sivapackia Ganapathiappan, Nag B. Patibandla
  • Patent number: 11935901
    Abstract: A display panel has a first region and a second region on side(s) thereof, a light transmittance of the first region is greater than that of the second region. The display panel includes pixels, first wirings arranged in a second direction that intersect a first region, and second wirings arranged in the first direction, all of which are in the first region and the second region. The first wirings and the second wirings are electrically connected to the pixels. First wirings passing through the first region are divided into first wiring groups, and first wirings in each first wiring group are gathered in the first region to constitute a first gathering portion. A distance between two adjacent first wirings in the second region is less than a distance between two adjacent first gathering portions, and is greater than a distance between two adjacent first wirings in the first gathering portion.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: March 19, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Mingche Hsieh
  • Patent number: 11929431
    Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: March 12, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kuang Hsieh, Shih-Hung Tsai
  • Patent number: 11929364
    Abstract: Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. In one case, a semiconductor structure includes a substrate and a low dielectric constant material region in the substrate. The low dielectric constant material region is positioned between a first device area in the semiconductor structure and a second device area in the semiconductor structure. The semiconductor structure also includes a III-nitride material layer over the substrate. The III-nitride material layer extends over the substrate in the first device area, over the low dielectric constant material region, and over the substrate in the second device area. The semiconductor structure can also include a first device formed in the III-nitride material layer in the first device area, a second device in the III-nitride material layer in the second device area, and an interconnect formed over the low dielectric constant material region.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: March 12, 2024
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Gabriel R. Cueva, Timothy E. Boles, Wayne Mack Struble
  • Patent number: 11908864
    Abstract: In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Chen, Chih-Hung Hsieh, Jhon Jhy Liaw
  • Patent number: 11903265
    Abstract: An organic light emitting diode display includes a plurality of first signal lines, a first insulating layer covering the first signal lines, a plurality of second signal lines on the first insulating layer and crossing the first signal lines, and a plurality of pixels connected to the first signal lines and the second signal lines. A groove in the first insulating layer separates adjacent ones of the pixels and a filling material in the groove.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Min-Sung Kim, Thanh Tien Nguyen, Ki Ju Im
  • Patent number: 11894389
    Abstract: Provided is a display substrate, a method for preparing the same, and a display device. The display substrate includes a pad bending region. In the pad bending region, the display substrate includes a base, and an inorganic insulating layer and a metal layer laminated on the base. The metal layer includes a plurality of discrete metal wires. The inorganic insulating layer includes a plurality of discrete first inorganic insulating layers, each of which is arranged between each of the plurality of discrete metal wires and the base.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: February 6, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Wang, Zhifeng Zhan, Yanxin Wang, Shuquan Yang, Jiafan Shi, Peng Huang
  • Patent number: 11887992
    Abstract: A substrate and a display device are provided. A first film layer of the substrate is formed on a third film layer and patterned to form a target pattern. A second film layer is formed on the third film layer and the first film layer. Within a distribution area of the target pattern, film edges of the first film layer are formed with protrusion structures facing the second film layer. Based on the protrusion structures, a deformable margin of the first film layer and the second film layer at a stacking position is increased, and a pattern of the second film layer is thus prevented from being cracked to generate cracks.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: January 30, 2024
    Assignee: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventor: Yuanke Huang
  • Patent number: 11881505
    Abstract: A semiconductor structure includes a plurality of fins on a semiconductor substrate, the plurality of fins including an alternating sequence of a first nanosheet made of epitaxially grown silicon and a second nanosheet made of epitaxially grown silicon germanium, and a shallow trench isolation region within the semiconductor substrate adjacent to the plurality of fins. The shallow trench isolation region including a recess within the substrate filled with a first liner, a second liner directly above the first liner, a third liner directly above the second liner, and a dielectric material directly above the third liner. The first liner is made of a first oxide material, the third liner is made of a nitride material, and the second liner is made of a second oxide material that creates a dipole effect for neutralizing positive charges within the third liner and positive charges between the third liner and the first liner.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: January 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Xin Miao, Alexander Reznicek, Jingyun Zhang
  • Patent number: 11881480
    Abstract: Semiconductor structure and method of forming semiconductor structure are provided. The semiconductor structure includes a substrate, a first isolation structure, and a first nanostructure and a second nanostructure on two sides of the first isolation structure. The semiconductor structure also includes a second isolation structure, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure. A top of the second isolation structure is lower than a top of the first isolation structure. The semiconductor structure also includes a first gate structure and a second gate structure. The first gate structure and the second gate structure expose a top surface of the first isolation structure. The semiconductor structure also includes a third gate structure and a fourth gate structure. The third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: January 23, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Jian Chen, Shiliang Ji, Haiyang Zhang
  • Patent number: 11876086
    Abstract: A display panel includes a substrate and display pixels. The display pixels are disposed on the substrate, and each of the display pixels includes pad sets, light-emitting devices, a first connecting wire, a second connecting wire, and first cutting regions. Each pad set has a first pad and a second pad. The light-emitting devices are electrically bonded to at least part of the pad sets. The first connecting wire is electrically connected to the first pads of a plurality of first pad sets of the pad sets. The second connecting wire is electrically connected to the second pads of the pad sets. The first cutting regions are disposed on one side of each of the first pad sets. Two first connecting portions of the first connecting wire and the second connecting wire connecting each of the first pad sets are located in one of the first cutting regions.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: January 16, 2024
    Assignee: Au Optronics Corporation
    Inventors: Cheng-He Ruan, Jian-Jhou Tseng, Chih-Yuan Hou
  • Patent number: 11876103
    Abstract: A display panel includes a plurality of sub-pixel structures and a plurality of transfer elements. The sub-pixel structures include a plurality of first sub-pixel structures. A data line of each of the first sub-pixel structures is disposed adjacent to a corresponding transfer element, and a scan line of each of the first sub-pixel structures is electrically connected to the corresponding transfer element. The first sub-pixel structures include a plurality of first-type sub-pixel structures and a plurality of second-type sub-pixel structures. When the display panel displays a grayscale picture, each of the first-type sub-pixel structures has first brightness, each of the second-type sub-pixel structures has second brightness. The first brightness is less than the second brightness. A total number of the first sub-pixel structures of the display panel is A, a number of the first-type sub-pixel structures in the first sub-pixel structures is a, and 50%<(a/A)<100%.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: January 16, 2024
    Assignee: AUO Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Ya-Ling Hsu, Chen-Hsien Liao
  • Patent number: 11869981
    Abstract: The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. One embodiment of the present invention is a semiconductor device which includes a gate electrode, an insulating film over the gate electrode, an oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film include the same element. The second oxide semiconductor film includes a region having lower crystallinity than one or both of the first oxide semiconductor film and the third oxide semiconductor film.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Yasutaka Nakazawa
  • Patent number: 11855160
    Abstract: A thin film transistor structure, a gate driver on array (GOA) circuit and a display device are provided. The thin film transistor structure defines a plurality of thin film transistors by patterning an active layer. Therefore, when a defect appears in the gate insulating layer of one of the plurality of thin film transistors and a leakage path is formed, other thin film transistors will not be affected. Therefore, a problem of functional failure of a whole thin film transistor structure can be avoided.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: December 26, 2023
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Gongtan Li, Hyunsik Seo
  • Patent number: 11847284
    Abstract: A transparent electrode member includes a translucent base, and first transparent electrodes that are arranged side by side in a first direction on a first surface of the base. An insulating layer does not overlap partial regions PR when viewed in the direction of the normal to the first surface. A rectangular region in which a part other than the conductive portion is composed of the partial regions over the entire part is defined as a first rectangular region, a rectangular region in which at least the insulating layer is contained is defined as a second rectangular region, and a relationship between an area Sa of the part other than the conductive portion in the first rectangular region and an area Sb of a part other than the conductive portion in the second rectangular region satisfies Sa/Sb=1±0.3.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: December 19, 2023
    Assignee: Alps Alpine Co., Ltd.
    Inventors: Toru Takahashi, Masayoshi Takeuchi
  • Patent number: 11843002
    Abstract: A transistor structure may include a first electrode, a second electrode, a third electrode, a substrate, and a semiconductor member. The semiconductor member overlaps the third electrode and includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion directly contacts the first electrode, is directly connected to the third semiconductor portion, and is connected through the third semiconductor portion to the second semiconductor portion. The second semiconductor portion directly contacts the second electrode and is directly connected to the third semiconductor portion. A minimum distance between the first semiconductor portion and the substrate is unequal to a minimum distance between the second semiconductor portion and the substrate.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: December 12, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Sup Lee, Jung Hun Noh, Keun Kyu Song, Sang Hee Jang, Byung Seok Choi
  • Patent number: 11844264
    Abstract: Systems and methods are described for a display panel and a method of manufacturing the display panel. The systems and methods may provide for a substrate having a first surface and a second surface that face each other, a display unit including an organic light-emitting device arranged on the first surface of the substrate; and a thin-film encapsulation layer arranged on the display unit to shield the display unit, wherein an edge of the first surface or an edge of the second surface are inclined with respect to the first surface or the second surface. The inclined surfaces are designed to prevent damage to the display due to fine cracks during the manufacturing process as the display panel is trimmed or cut from a single base member. A display panel having improved strength characteristics may be manufactured, as well.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: December 12, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Wonje Jo, Youngji Kim, Yiseul Um, Younghoon Lee, Jiwon Jung, Youngseo Choi, Dongwon Han