Abstract: Microelectromechanical system (MEMS) inertial sensors exhibiting reduced parasitic capacitance are described. The reduction in the parasitic capacitance may be achieved by forming localized regions of thick dielectric material. These localized regions may be formed inside trenches. Formation of trenches enables an increase in the vertical separation between a sense capacitor and the substrate, thereby reducing the parasitic capacitance in this region. The stationary electrode of the sense capacitor may be placed between the proof mass and the trench. The trench may be filled with a dielectric material. Part of the trench may be filled with air, in some circumstances, thereby further reducing the parasitic capacitance. These MEMS inertial sensors may serve, among other types of inertial sensors, as accelerometers and/or gyroscopes. Fabrication of these trenches may involve lateral oxidation, whereby columns of semiconductor material are oxidized.

Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.

Abstract: The present technology relates to a photoelectric conversion element, a measuring method of the same, a solid-state imaging device, an electronic device, and a solar cell capable of further improving a quantum efficiency in a photoelectric conversion element using a photoelectric conversion layer including an organic semiconductor material. The photoelectric conversion element includes two electrodes forming a positive electrode (11) and a negative electrode (14), at least one charge blocking layer (13, 15) arranged between the two electrodes, and a photoelectric conversion layer (12) arranged between the two electrodes. The at least one charge blocking layer is an electron blocking layer (13) or a hole blocking layer (15), and a potential of the charge blocking layer is bent. The present technology is applied to, for example, a solid-state imaging device, a solar cell, and the like having a photoelectric conversion element.

Abstract: Provided are a display panel, a manufacturing method thereof, and a display device. A first display region of the display panel includes first pixel units and first drive circuits, a second display region includes second pixel units and second drive circuits, wherein a pixel unit density of the first pixel units is less than a pixel unit density of the second pixel units, a number of first additional transistors in the first drive circuit is less than a number of second additional transistors in the second drive circuit, and an area of the orthographic projection of a channel area of the first drive transistor on the base substrate is less than an area of the orthographic projection of a channel area of the second drive transistor on the base substrate.

Abstract: A display device includes a flexible substrate, a plurality of TFTs, a first electrode arranged between a channel of one of the plurality of TFTs and the flexible substrate, at least one inorganic insulating film arranged between one of the plurality of TFTs and the first electrode, a second electrode arranged on the opposite side to the side where one of the plurality of TFTs is arranged with respect to the first electrode, and an organic insulating film arranged between the first electrode and the second electrode.

Abstract: An electronic device includes a substrate, multiple transversal signal lines, a first vertical signal line, a second vertical signal line, a shielding wire, and multiple pixel structures. The first vertical signal line is intersected with the transversal signal lines. The second vertical signal line is intersected with the transversal signal lines and connected to one of the transversal signal lines. An orthogonal projection of the shielding wire on the substrate is located between an orthogonal projection of the first vertical signal line and an orthogonal projection of the second vertical signal line on the substrate. One of the pixel structures is surrounded by a corresponding one of the transversal signal lines and the second vertical signal line and includes an active device. A gate and a source of the active device is electrically connected to the corresponding one transversal signal line and the first vertical signal line respectively.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a substrate, at least a portion of one or more of the fins providing one or more channels for one or more fin field-effect transistors. The method also includes forming a plurality of active gate structures over the fins, forming at least one single diffusion break trench between a first one of the active gate structures and a second one of the active gate structures, and forming at least one double diffusion break trench between a third one of the active gate structures and a fourth one of the active gate structures. The double diffusion break trench has a stepped height profile in the substrate, the stepped height profile comprising a first depth with a first width and a second depth less than the first depth with a second width greater than the first width.

Abstract: An array substrate includes a base substrate including a first surface, a plurality of first wirings disposed on the first surface of the base substrate and extending in a first direction, and at least one first light-shielding strip disposed above the first surface of the base substrate. Wirings passing through the sensing component region in the plurality of first wirings are selected first wirings, the selected first wirings are divided into at least one group, each group includes at least two adjacent selected first wirings, and selected first wirings in each group are gathered in the sensing component region to form a first gathering portion. An orthographic projection of each first gathering portion on the first surface of the base substrate is within a range of an orthographic projection of a corresponding first light-shielding strip on the first surface of the base substrate.

Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.

Abstract: A photoelectric converting device including: a semiconductor layer with a front surface and a back surface, the semiconductor layer including a photoelectric conversion portion; a wire structure including an insulating film, the wire structure being disposed on the front surface of the semiconductor layer; a first insulator portion disposed in a trench provided in the semiconductor layer; and a second insulator portion disposed between the first insulator portion and the insulating film, wherein the first insulator portion has a maximum width larger than a maximum width of the second insulator portion.

Abstract: A method for manufacturing an active matrix substrate includes: (A) a step of forming a laminated film including a lower conductive film, a lower insulating film, and a semiconductor film in this order on a substrate; (B) a step of forming a first resist layer; (C) a step of performing a patterning on the laminated film, the step including, in the first formation region, forming the first substructure including a first lower conductive layer, a first lower insulating layer, and a first semiconductor layer respectively formed from the lower conductive film, the lower insulating film, and the semiconductor film, and (D) a step of forming source and drain electrodes electrically connected to the first semiconductor layer.

Abstract: The transparent display includes a substrate and a plurality of frame traces. The substrate includes a transparent display region and a frame region defined on a left side, a right side, and an upper side of the transparent display region. The plurality of frame traces are disposed in the frame region, and each frame trace includes a hollow portion and a conductive portion surrounding the hollow portion. B disposing the hollow portion in each frame trace to improve a transmittance of each frame trace, thereby improving a transparency of the frame region, reducing a risk of disconnection, and improving a product yield.

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

Abstract: The present disclosure provides an array substrate, including: a base, and at least one lead structure disposed on the base. The lead structure includes a first conductive structure and a conductive semiconductor structure, and an orthographic projection of the conductive semiconductor structure on the base at least partially overlaps an orthographic projection of the first conductive structure on the base.

Abstract: A method of fabricating suspended beam silicon carbide microelectromechanical (MEMS) structure with low capacitance and good thermal expansion match. A suspended material structure is attached to an anchor material structure that is direct wafer bonded to a substrate. The anchor material structure and the suspended material structure are formed from either a hexagonal single-crystal SiC material, and the anchor material structure is bonded to the substrate while the suspended material structure does not have to be attached to the substrate. The substrate may be a semi-insulating or insulating SiC substrate. The substrate may have an etched recess region on the substrate first surface to facilitate the formation of the movable suspended material structures. The substrate may have patterned electrical electrodes on the substrate first surface, within recesses etched into the substrate.

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

Abstract: A display panel includes first signal lines, second signal lines, first conductive patterns, second conductive patterns, at least one first switching unit and at least one second switching unit. An area of the first signal line is greater than that of the second signal line. Each first signal line is electrically connected to at least one first conductive pattern through at least one first switching unit. Each second signal line is electrically connected to at least one second conductive pattern through at least one second switching unit. The first switching unit includes at least one first thin film transistor, and the second switching unit includes at least one second thin film transistor. A channel width-to-length ratio of each first thin film transistor is greater than that of each second thin film transistor.

Abstract: A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.

Abstract: A method of manufacturing a display substrate, a display substrate and a display panel are provided. The method of manufacturing a display substrate includes: infiltrating an etching point of a film group with an etching solution, to form an infiltration groove at the etching point of a film group; and patterning a remaining part of the film group at the infiltration groove, to obtain a via hole penetrating the remaining part of the film group.

Abstract: A display panel and a method for manufacturing a display panel that includes a front side and a back side, the display panel including a substrate having a plurality of electrical components provided on a front side of the substrate and integrated circuits connected to the plurality of electrical components, the integrated circuits being embedded in the substrate. A plurality of edge contacts is also provided along edges of the substrate, where the plurality of edge contacts is electrically connected with the integrated circuits. An electrically conductive layer covers at least a part of the front side of the substrate and surrounds the plurality of electrical components, where the electrically conductive layer does not physically contact the embedded integrated circuits and provides electromagnetic interference (EMI) shielding to different components of the display panel.