Abstract: A display panel includes a plurality of sub-pixel structures and a plurality of transfer elements. The sub-pixel structures include a plurality of first sub-pixel structures. A data line of each of the first sub-pixel structures is disposed adjacent to a corresponding transfer element, and a scan line of each of the first sub-pixel structures is electrically connected to the corresponding transfer element. The first sub-pixel structures include a plurality of first-type sub-pixel structures and a plurality of second-type sub-pixel structures. When the display panel displays a grayscale picture, each of the first-type sub-pixel structures has first brightness, each of the second-type sub-pixel structures has second brightness. The first brightness is less than the second brightness. A total number of the first sub-pixel structures of the display panel is A, a number of the first-type sub-pixel structures in the first sub-pixel structures is a, and 50%<(a/A)<100%.

Abstract: The present disclosure illustrates a repair method for an active matrix substrate. The repair method includes steps: performing the broken-line inspection process to inspect whether the broken line exists on the first and second gate lines; if one first gate line is inspected to be broken, performing a source line repair-section forming process to cut off the cut portions of the second source lines disposed at two sides of a pixel electrode corresponding to a broken location of the first gate line, to form source line repair sections overlapping with the broken first gate line and the second gate line; performing a gate line repair-section forming process on the second gate line, adjacent to the broken first gate line, to cut off the cut portions of the second gate line to form a gate line repair section overlapping with the second source lines; and performing a connection process.

Abstract: According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.

Abstract: A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.

Abstract: The present invention provides a display including: a substrate; a plurality of data lines disposed above the substrate; and a pixel electrode disposed above the plurality of data lines, and including: at least one first trunk and a plurality of second trunks extending along a first direction; a plurality of first branches; and a plurality of second branches, wherein distal ends of the plurality of first branches and distal ends of the plurality of second branches are staggered and connected to each other at positions corresponding to the plurality of data lines.

Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.

Abstract: To enhance a charge transfer efficiency in a transfer gate having a vertical gate electrode. A solid-state imaging element includes a photoelectric conversion section, a charge accumulating section, and a transfer gate. The photoelectric conversion section is formed in a depth direction of a semiconductor substrate, and generates charges corresponding to a quantity of received light. The charge accumulating section accumulates the charges generated by the photoelectric conversion section. The transfer gate transfers the charges generated by the photoelectric conversion section to the charge accumulating section. The transfer gate includes a plurality of vertical gate electrodes which is filled to a predetermined depth from an interface of the semiconductor substrate, and at least a part of a diameter is different in the depth direction of the semiconductor substrate.

Abstract: A pixel structure and a manufacturing method therefor, an array substrate, and a display device are provided. The pixel structure includes a pixel electrode, an active layer, a source/drain electrode layer, and a common electrode which are located on a base substrate. The pixel electrode is located between the base substrate and the common electrode. The source/drain electrode layer includes a first electrode and a second electrode which are electrically connected to the active layer, and the second electrode is electrically connected to the pixel electrode. The active layer is located between the base substrate and the source/drain electrode layer. The active layer includes a first surface close to the source/drain electrode layer. The source/drain electrode layer includes a second surface close to the active layer. Partial edge of the first surface is aligned with partial edge of the second surface.

Abstract: A pixel array substrate, including gate elements and transfer elements, is provided. The gate elements include an n-th gate element and an m-th gate element. The transfer elements include a n-th transfer element and an m-th transfer element electrically connected to the n-th gate element and the m-th gate element respectively. A peripheral portion of each of the transfer elements includes a first straight section. A peripheral portion of the n-th transfer element further includes a first lateral section. The first lateral section of the n-th transfer element and the first straight section of the n-th transfer element respectively belong to a first conductive layer and a second conductive layer. A peripheral portion of the m-th transfer element crosses over the first lateral section of the peripheral portion of the n-th transfer element.

Abstract: A display panel and a method for manufacturing the same, and a display device is provided. The display panel includes a display area including a plurality of gate lines arranged spaced apart in a first direction and a non-display area including a first and a second non-display area. At least one of the first or the second non-display area includes: a gate driving area including a plurality of gate driving units arranged spaced apart in the first direction and connected to the gate lines, a length of at least one gate driving unit being smaller than a length of a pixel in the first direction; a dummy gate driving area including a plurality of dummy gate driving units arranged spaced apart in the first direction; and a first trace area including a plurality of first traces connected to the dummy gate driving units and an external circuit.

Abstract: A display panel, a manufacturing method and a repair method thereof are provided. The display panel includes a flexible substrate and a plurality of bent traces. The flexible substrate includes a display portion, a bent portion, and a bezel portion being arranged in order. The bezel portion and the display portion are stacked through a bending in the bent portion. The bent portion is provided with the plurality of bent traces. Material of the bent traces includes a first material, and the first material is a conductive material having a melting point lower than 250° C. By adding the first material with the low melting point to the bent traces, when the bent traces are broken, the first material can be melted to flow by heating, thereby repairing the broken traces among the bent traces, whereby realizing the self-repair of the bent traces, increasing the process yield and reducing the production loss.

Abstract: Embodiments of the present disclosure provide a flexible array substrate, a manufacturing method thereof, and a flexible display device, which relate to the field of display technology, and can reduce the difficulty of wiring, decrease the IR drop, and improve the problem that the wiring is prone to breakage when bent. The flexible array substrate includes a substrate, the substrate including a first sub-substrate and a second sub-substrate which are stacked, the second sub-substrate including at least one via hole; a wiring layer disposed between the first sub-substrate and the second sub-substrate; and a pixel array layer disposed on a side of the second sub-substrate facing away from the first sub-substrate; the wiring layer including a wiring, wherein the pixel array layer is electrically connected to the wiring through the at least one via hole.

Abstract: This application discloses a method for manufacturing a display panel, a display panel, and a display device. The display panel has a display area and a peripheral area. The display panel includes a first substrate, a second substrate, a plurality of pixel elements, a plurality of data lines and scanning lines, and a plurality of color filters. The first substrate includes a first shading layer, the first shading layer being formed between two neighboring pixel elements to block the data lines or the scanning lines. The display area includes an opening area and a non-opening area, and the first shading layer is arranged only in the non-opening area. The second substrate includes a second shading layer arranged corresponding to the first shading layer. Each of the data lines and the scanning lines is blocked by at least one of the first shading layer and the second shading layer.

Abstract: A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.

Abstract: An array substrate includes a base, a plurality of thin film transistors, a passivation layer, at least one reflective electrode, and at least one first connecting electrode. The array substrate has a display area. The thin film transistors are disposed in the display area on the base. The passivation layer covers the thin film transistors, and has at least one first via hole in the display area. The reflective electrode is disposed on a surface of the passivation layer facing away from the base, and is disposed in the display area and uncovers the first via hole. The first connecting electrode is disposed on a side of the reflective electrode away from the base. Each first connecting electrode is connected to a corresponding reflective electrode, and is connected to a source or a drain of a corresponding thin film transistor through a corresponding first via hole.

Abstract: A display panel, a display device, and a display system are provided. The display panel includes a plurality of conductive portions. Each of the conductive portions is respectively disposed between corresponding metal layers to be electrically connected in the display panel, and is used to electrically connect with the metal layers to be electrically connected. At least two conductive portions are provided between any two of the metal layers to be electrically connected. The at least two conductive portions are used for an electrical connection to realize multi-point connection of different metal layers, which improves a reliability in a conversion of different metal layers.

Abstract: An array substrate having a plurality of subpixels is provided. In a respective one of the plurality of subpixels, the array substrate includes a base substrate; and a thin film transistor on the base substrate. The thin film transistor includes a gate electrode, a source electrode, and a drain electrode. The drain electrode includes a first portion, a second portion, and a third portion connecting the first portion and the second portion. An orthographic projection of the first portion on the base substrate at least partially overlaps with an orthographic projection of a first gate line protrusion of a respective one of the plurality of gate lines on the base substrate. An orthographic projection of the second portion on the base substrate at least partially overlaps with an orthographic projection of a second gate line protrusion of the respective one of the plurality of gate lines on the base substrate.

Abstract: An array substrate, a display device, and a method for repairing a broken wire of an array substrate are disclosed. The array substrate includes a substrate, a plurality of sub-pixel units on the substrate, and a wire and a first conductive light-blocking pattern between two adjacent sub-pixel units of the plurality of sub-pixel units. The first conductive light-blocking pattern is electrically insulated from the wire, and the first conductive light-blocking pattern includes two first regions. Orthographic projections of the two first regions on the substrate overlap with an orthographic projection of the wire on the substrate.

Abstract: A semiconductor device includes a layer of a first semiconducting material, where the first semiconducting material is epitaxially grown to have a crystal structure of a first substrate. The semiconductor device further includes a layer of a second semiconducting material disposed adjacent to the layer of the first semiconducting material to form a heterojunction with the layer of the first semiconducting material. The semiconductor device further includes a first component that is electrically coupled to the heterojunction, and a second substrate that is bonded to the layer of the first semiconducting material.

Abstract: An organic light emitting diode display includes a flexible substrate including a folding area and a flat area, a first insulating layer on the flexible substrate having a first opening, a first conductor on the first insulating layer, and a second insulating layer covering the first conductor with the first insulating layer also having the first opening. The organic light emitting diode display further includes a second conductor on the second insulating layer, a third insulating layer covering the second conductor and the second insulating layer, and a filling material in the first opening. A thickness of the filling material in the first opening is less than a thickness from a bottom surface of the first insulating layer to an upper surface of the second insulating layer.