Patents Examined by Robert Huber
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Patent number: 9859223Abstract: Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a dicing street disposed between the first and the second chip. A first and a second metal level are disposed over the dicing street, wherein the second metal level is disposed above the first metal level. A first alignment mark is disposed in the first metal level above a first portion of the dicing street, and first metal features disposed in the second metal level above the first portion of the dicing street.Type: GrantFiled: July 6, 2015Date of Patent: January 2, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hsien-Wei Chen
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Patent number: 9859399Abstract: A lateral diffused semiconductor device is disclosed, including: a substrate; a first isolation and a second isolation comprising at least portions disposed in the substrate to define an active area; a first drift region and a second drift region disposed in the active area, wherein the first drift region is disposed in the second drift region; a gate structure on the substrate; a source region in the first drift region; a drain region in the second drift region; and a ring-shaped field plate on the substrate, wherein the ring-shaped field plate surrounds at least one of the source and the drain region.Type: GrantFiled: November 5, 2013Date of Patent: January 2, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Sue-Yi Chen, Chien-Hsien Song, Chih-Jen Huang
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Patent number: 9859342Abstract: An organic light emitting diode display that maintains a luminance distribution characteristic of each pixel at the side substantially similar to a luminance distribution characteristic of each pixel at the front of the OLED display by improving a twist of a lateral color with respect to a front color. The organic light emitting diode display includes a substrate, a driving wire disposed on the substrate, a color filter disposed on the driving wire. The color filter includes a blue color filter, a red color filter, and a green color filter formed on the driving wire; and an organic light emitting diode disposed on the color filter, where a width of the blue color filter is greater than a width of the red color filter or the green color filter.Type: GrantFiled: August 27, 2013Date of Patent: January 2, 2018Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Min-Woo Kim, Jae-Ik Lim, Man-Seob Choi, Won-Gyun Kim, Won-Sang Park
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Patent number: 9859347Abstract: An organic light emitting diode (OLED) display device and a method of manufacturing the same. The device includes a substrate, a thin film transistor (TFT) on the substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode, a first pixel electrode coupled to one of the source and drain electrodes, a rough portion on the first pixel electrode, a second pixel electrode on the rough portion and having a rough pattern, an intermediate layer on the second pixel electrode including an organic emission layer (EML), and an opposing electrode on the intermediate layer.Type: GrantFiled: August 28, 2013Date of Patent: January 2, 2018Assignee: Samsung Display Co., Ltd.Inventors: Seong-Hyun Jin, Jae-Hwan Oh, Yeoung-Jin Chang, Se-Hun Park, Won-Kyu Lee, Jae-Beom Choi
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Patent number: 9853158Abstract: Embodiments are directed to forming a structure comprising at least one fin, a gate, and a spacer, applying an annealing process to the structure to create a gap between the at least one fin and the spacer, and growing an epitaxial semiconductor layer in the gap between the spacer and the at least one fin.Type: GrantFiled: June 30, 2016Date of Patent: December 26, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-chen Yeh
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Patent number: 9847281Abstract: Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process.Type: GrantFiled: June 30, 2015Date of Patent: December 19, 2017Assignee: STMICROELECTRONICS, INC.Inventor: Jefferson Talledo
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Patent number: 9842972Abstract: A radiation-emitting semiconductor component includes a semiconductor body having an active layer which emits electromagnetic radiation of a first wavelength ?1 in a main radiation direction, and having a luminescence conversion layer, which converts at least part of the emitted radiation into radiation of a second wavelength ?2, which is greater than the first wavelength ?1.Type: GrantFiled: December 13, 2010Date of Patent: December 12, 2017Assignee: OSRAM Opto Semiconductors GmbHInventors: Krister Bergenek, Mikael Ahlstedt, Ute Liepold
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Patent number: 9837440Abstract: A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.Type: GrantFiled: February 7, 2014Date of Patent: December 5, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Hong He, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo
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Patent number: 9825013Abstract: A light emitting device array including a circuit substrate and a plurality of device layers is provided. The circuit substrate includes a plurality of bonding pads and a plurality of conductive bumps located over the bonding pads. The device layers are capable of emitting different colored lights electrically connected with the circuit substrate through the conductive bumps and the bonding pads. The device layers capable of emitting different colored lights have different thicknesses and the conductive bumps bonded with the device layers capable of emitting different colored lights have different heights such that top surfaces of the device layers capable of emitting different colored lights are located on a same level of height.Type: GrantFiled: December 16, 2015Date of Patent: November 21, 2017Assignee: Industrial Technology Research InstituteInventors: Wen-Yung Yeh, Chia-Hsin Chao, Ming-Hsien Wu, Kuang-Yu Tai
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Patent number: 9818872Abstract: A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source/drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source/drain feature.Type: GrantFiled: June 30, 2015Date of Patent: November 14, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 9818605Abstract: An Oxide TFT, a preparation method thereof, an array substrate and a display device are described. The method includes forming a gate electrode, a gate insulating layer, a channel layer, a barrier layer, as well as a source electrode and a drain electrode on a substrate; the channel layer is formed by depositing an amorphous oxide semiconductor film in a first mixed gas containing H2, Ar and O2. By depositing a channel layer in a first mixed gas containing H2, Ar and O2, the hysteresis phenomenon of the TFT can be mitigated effectively to improve the display quality of the display panel.Type: GrantFiled: July 2, 2013Date of Patent: November 14, 2017Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Changjiang Yan, Tiansheng Li, Shaoying Xu, Zhenyu Xie, Xu Chen
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Patent number: 9818849Abstract: A first insulating film in contact with an oxide semiconductor film and a second insulating film are stacked in this order over an electrode film of a transistor including the oxide semiconductor film, an etching mask is formed over the second insulating film, an opening portion exposing the electrode film is formed by etching a portion of the first insulating film and a portion of the second insulating film, the opening portion exposing the electrode film is exposed to argon plasma, the etching mask is removed, and a conductive film is formed in the opening portion exposing the electrode film. The first insulating film is an insulating film whose oxygen is partly released by heating. The second insulating film is less easily etched than the first insulating film and has a lower gas-permeability than the first insulating film.Type: GrantFiled: October 29, 2014Date of Patent: November 14, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shinya Sasagawa, Hiroshi Fujiki, Yoshinori Ieda
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Patent number: 9806172Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.Type: GrantFiled: October 3, 2015Date of Patent: October 31, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Ming Zhu
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Patent number: 9799671Abstract: Dielectric degradation and electrical shorts due to fluorine radical generation from metallic electrically conductive lines in a three-dimensional memory device can be reduced by forming composite electrically conductive layers and/or using of a metal oxide material for an insulating spacer for backside contact trenches. Each composite electrically conductive layer includes a doped semiconductor material portion in proximity to memory stack structures and a metallic material portion in proximity to a backside contact trench. Fluorine generated from the metallic material layers can escape readily through the backside contact trench. The semiconductor material portions can reduce mechanical stress.Type: GrantFiled: April 7, 2015Date of Patent: October 24, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Jayavel Pachamuthu, Matthias Baenninger, Stephen Shi, Johann Alsmeier
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Patent number: 9793168Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.Type: GrantFiled: December 21, 2015Date of Patent: October 17, 2017Assignee: GLOBALFOUNDRIES INC.Inventor: David P. Brunco
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Patent number: 9786796Abstract: A semiconductor device having first through third layers. The first layer has a conductivity type that is different from a conductivity type of the second layer. A peak value of an impurity concentration of a portion of the third layer is greater than a peak value of an impurity concentration of the second layer. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.Type: GrantFiled: April 16, 2015Date of Patent: October 10, 2017Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Katsumi Nakamura
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Methods, devices, and systems related to forming semiconductor power devices with a handle substrate
Patent number: 9768271Abstract: Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.Type: GrantFiled: February 22, 2013Date of Patent: September 19, 2017Assignee: Micron Technology, Inc.Inventors: Martin F. Schubert, Vladimir Odnoblyudov, Cem Basceri -
Patent number: 9768408Abstract: An organic light emitting diode display and a manufacturing method thereof are provided. The organic light emitting diode display includes a first substrate, a second substrate, a plurality of organic light emitting diodes, and a frit layer. The organic light emitting diodes are disposed on the first substrate, and the frit layer adheres the first substrate and the second substrate to each other. The frit layer includes a first porous region having pores, a second porous region having pores, and a third porous region having pores. The number of the pores of the first porous region with a diameter of larger than or equal to 4 ?m and smaller than or equal to 15 ?m is greater than the number of the pores of the second porous region with the above-mentioned diameter range.Type: GrantFiled: May 27, 2015Date of Patent: September 19, 2017Assignee: INNOLUX CORPORATIONInventors: Hao-Jung Huang, Kuang-Pin Chao, Yang-Chen Chen
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Patent number: 9768125Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor layer having an element region and an outer peripheral region, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The metal layer extends to cover at least a portion of a sidewall of the step portion. The method of manufacturing the semiconductor device further includes dividing the semiconductor layer into element regions on an outside of the step portion when viewed from the element region.Type: GrantFiled: May 14, 2015Date of Patent: September 19, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toru Hiyoshi, Taku Horii
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Patent number: 9733148Abstract: Embodiments of the present invention provide moisture measuring systems and methods. According to one embodiment of the present invention, a sealable compartment is used in which a specimen containing liquid can be inserted, such that all of the specimen is contained within the compartment. The relative humidity in the compartment is measured over a duration of time, which can be used to calculate the amount of liquid leaked by the specimen. Embodiments of the present invention can be utilized, for example, to calculate the leakage rate of water-carrying hardware of a cooling system, without having to create a membrane or other isolated sample of materials.Type: GrantFiled: December 3, 2014Date of Patent: August 15, 2017Assignee: International Business Machines CorporationInventors: Michael G. Betro, Michael J. Ellsworth, Jr., Enrico A. Romano, Prabjit Singh, Jing Zhang