Abstract: An organic EL element including: a TFT substrate having a TAOS-TFT; and an organic EL unit having a lower electrode. The lower electrode includes an aluminum containing metal layer, a transition metal containing oxide layer disposed between the aluminum containing metal layer and the TFT substrate, and an aluminum containing oxide layer disposed between the aluminum containing metal layer and the transition metal containing oxide layer and in contact with both the aluminum containing metal layer and the transition metal containing oxide layer. The aluminum containing oxide layer contains aluminum oxide. The transition metal containing oxide layer contains tungsten oxide and has a density of 6.5 g/cm3 or more.

Abstract: A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor. A through via penetrates through the semiconductor substrate. A Redistribution Line (RDL) is disposed over the plurality of dielectric layers, wherein the RDL is electrically coupled to the through via. A polymer layer covers the RDL.

Abstract: A semiconductor device includes a first substrate including a plurality of first pads disposed on a first surface of the first substrate, a second substrate including a plurality of second pads disposed on a second surface of the substrate, a plurality of conductive bumps bonded the plurality of first pads with the plurality of second pads correspondingly, a solder bracing material disposed on the first surface and surrounded the plurality of conductive bumps, an underfill material surrounded the plurality of conductive bumps and disposed between the solder bracing material and the second surface, and a rough interface between the solder bracing material and the underfill material; wherein the rough interface includes a plurality of protruded portions and a plurality of recessed portions.

Abstract: A display device and a method of manufacturing the same are disclosed. In one aspect, the display device includes a plurality of pixels, wherein each pixel includes a scan line extending in a first direction. Each pixel also includes a data line extending in a second direction crossing the first direction and a driving thin-film transistor (TFT) formed adjacent to the data line and including a gate electrode, a source electrode, and a drain electrode. The pixel also includes an interlayer insulating layer formed between the data line and the driving TFT, and a first through hole is formed in the interlayer insulating layer to be adjacent to the data line and the gate electrode. Each pixel also includes a driving voltage line formed adjacent to the data line and including a first portion formed in the first through hole and formed on the interlayer insulating layer.

Abstract: According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.

Abstract: Disclosed herein is a method for dicing a wafer, the method comprising forming a molding compound layer over each of one or more dies disposed on a wafer, the one or more dies separated by scribe lines, the molding compound layer having gaps over the respective scribe lines. The wafer is separated into individual dies along the gaps of the molding compound in the scribe lines. Separating the wafer into individual dies comprises cutting at least a portion of the substrate with a laser. Forming the molding compound layer comprises applying a stencil over the one or more dies and using the stencil to form the molding compound layer.

Abstract: An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation.

Abstract: A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.

Abstract: Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed.

Abstract: A three-dimensional (3D) semiconductor memory device may include a substrate including a cell array region and a connection region, an electrode structure including pluralities of first and second electrodes that are vertically and alternately stacked on a surface of the substrate, extending in a first direction that is parallel to the surface of the substrate, and may include a stair step structure on the connection region, first and second string selection electrodes that extend in the first direction on the electrode structure and spaced apart from each other in a second direction that is parallel to the surface of the substrate and perpendicular to the first direction. The first and second string selection electrodes may each include an electrode portion on the cell array region and a pad portion that extends from the electrode portion in the first direction and on the connection region.

Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

Abstract: Provided are a power device having an improved field stop layer and a method of manufacturing the same. The method can include performing a first ion implant process by implanting impurity ions of a first conductive type into a front surface of a semiconductor substrate to form an implanted field stop layer where the semiconductor substrate is the first conductive type. The method can include performing a second ion implant process by implanting impurity ions of the first conductive type into a first part of the implanted field stop layer such that an impurity concentration of the first part of the implanted field stop layer is higher than an impurity concentration of a second part of the implanted field stop layer.

Abstract: Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.

Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

Abstract: The present invention provides a substrate (1) with a bulk layer (3) and a buffer layer (4) having a thickness of less than 2 ?m arranged on the bulk layer (3) for growth of a multitude of nanowires (2) oriented in the same direction on a surface (5) of the buffer layer (4). A nanowire structure, a nanowire light emitting diode comprising the substrate (1) and a production method for fabricating the nanowire structure is also provided. The production method utilizes non-epitaxial methods for forming the buffer layer (4).

Abstract: A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle.

Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.

Abstract: An isolation structure formed in a semiconductor substrate of a first conductivity type includes a floor isolation region of a second conductivity type opposite to the first conductivity type submerged in the substrate. A first trench extends downward from a surface of the substrate and overlaps onto the floor isolation region. The first trench includes walls lined with a dielectric material and contains a conductive material. The first trench and the floor isolation region electrically isolate a pocket of the first conductivity type from the substrate.

Abstract: An oxide semiconductor film with a low density of defect states is formed. In addition, an oxide semiconductor film with a low impurity concentration is formed. Electrical characteristics of a semiconductor device or the like using an oxide semiconductor film is improved. A semiconductor device including a capacitor, a resistor, or a transistor having a metal oxide film that includes a region; with a transmission electron diffraction measurement apparatus, a diffraction pattern with luminescent spots indicating alignment is observed in 70% or more and less than 100% of the region when an observation area is changed one-dimensionally within a range of 300 nm.

Abstract: A manufacturing method for a micromechanical sensor device and a corresponding micromechanical sensor device. The method includes providing a substrate including at least one first through a fourth parallel trenches; depositing a layer onto the front side, the trenches being sealed, and structuring the layer, contact structures being formed in the layer above the second and fourth trenches; oxidizing of outwardly free-standing side surfaces of the contact structures as well as of the second and fourth trenches, at least in areas; depositing and structuring a first metallic contacting material, the contact structures being filled with the first metallic contacting material, at least in areas; opening the second trench and the fourth trench; galvanic deposition of a second metallic contacting material into the second and fourth trenches, resulting in the formation of a pressure-sensitive capacitive capacitor structure; and opening the first trench from the front side of the substrate.