Abstract: Provided is a system for constructing mobile electric energy interconnection. The system includes at least one mobile electric energy exchange device, a mobile electric energy interconnection management platform and at least one stationary electric energy interconnection device. The mobile electric energy interconnection management platform is configured to match the at least one mobile electric energy exchange device with the at least one stationary electric energy interconnection device, and push a matching result to the at least one mobile electric energy exchange device and the at least one stationary electric energy interconnection device. Also provided is a method for constructing mobile electric energy interconnection, a data testing method and device, and a computer readable storage medium.

Abstract: Voltage monitoring circuit having an analog reset signal generator to generate a reset signal and coupled to a voltage to be monitored; first register to store a first state bit and coupled to the voltage to be monitored; second register connected in parallel to the first register, redundant to the first register, to store a second state bit, and coupled to the voltage to be monitored; logic coupled to the first and second registers and to determine a state control signal from the first and second state bits, and a second reset signal; and OR logic to receive the following signals on the input side and process them with one another according to an OR operation: a first reset signal generated by the analog reset signal generator and the second reset signal, so that a reset control signal is generated and fed to reset inputs of the registers.

Abstract: A delay circuit includes a voltage/current conversion unit, a capacitor, and an output logic unit. The voltage/current conversion unit receives an input signal and generates current based on a voltage level of the input signal, and the generated current is proportional to the voltage level of the input signal. The capacitor is electrically connected to the voltage/current conversion unit and configured to receive the current generated by the voltage/current conversion unit, to charge. The output logic unit is electrically connected to the capacitor configured to receive a voltage signal on a terminal of the capacitor and generate an output signal based on the voltage signal, a delay time between a transition time point of the input signal and a transition time point of the output signal is not related to the voltage level of the input signal.

Abstract: A wiring system for a vehicle is specified, which has a voltage source and an electrical load, whereby a need for the electrical load depends on an external condition. Furthermore, the wiring system has a load path with an electrical line, which connects the voltage source to the electrical load, and a first switching element, which is arranged in the load path, for disconnecting the electrical load from the voltage source, wherein a working range of the external condition is defined, within which the function of the electrical load is reasonable, and a control unit is arranged, which is designed in such a way that a switching on of the electrical load is prevented if the external condition lies outside the working range. Furthermore, a method for the design of an electrical line of such a wiring system is given.

Abstract: There are provided a signal width repair circuit and method, and an electronic device. The signal width repair circuit includes: a delay circuit, configured to receive an input signal, and delay the input signal for a preset duration to obtain a delayed signal, the input signal being a high-level signal; a signal reconstruction circuit, configured to receive the input signal and the delayed signal, and repair the input signal and the delayed signal to obtain a repaired signal; and a signal selection circuit, configured to receive the input signal and the repaired signal and select one of the input signal and the repaired signal for output, to obtain a target signal that has a width satisfying a preset width, the preset duration being equal to or greater than a duration with the preset width.

Abstract: A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.

Abstract: A deskew system can be used to adjust signal characteristics such as pulse width and edge timing. In an example, a deskew system can include multiple timing control cells and each cell can operate in one of multiple different modes according to respective mode control signals. The modes can include at least a signal delay mode and a signal pulse width adjustment mode. In an example, a first cell in a deskew system can be configured to receive a test input signal at a first input node and, in response, provide a deskew output signal at a first output node. The deskew output signal can be based on the test input signal, a pulse width adjustment provided by the first cell, and on a delayed signal, corresponding to the input signal, that is provided by a subsequent cell in the series.

Abstract: A delay circuit and a delay structure are provided. The circuit includes: a first delay unit configured to delay a rising edge and/or a falling edge of a pulse signal, where, an input terminal of the first delay unit receives the pulse signal, and an output terminal of the first delay unit outputs a first delay signal, and a second delay unit, configured to delay the first delay signal, where an input terminal of the second delay unit is connected to the output terminal of the first delay unit, and an output terminal of the second delay unit outputs a second delay signal.

Abstract: This publication describes apparatuses and methods for driving a switching device and providing for the fast start-up of the switching device. In an aspect, the apparatus includes a driver circuit and a starter circuit. The driver circuit for applying control signals to a control terminal of the switching device when activated. The switching device is activatable to drive a load in an operating mode when a control signal above a threshold voltage is applied to the control terminal. The starter circuit is coupled to the control terminal and includes an energy store and a switch operable to discharge the energy store to deliver a start-up voltage above the threshold to the control terminal. As such, the switching device can be activated during a delay period before the driver circuit can generate a control signal above the threshold voltage after being activated.

Abstract: A driving circuit, including: a pull-up transistor and a pull-down transistor, where a first terminal of the pull-up transistor is connected with a power source, a second terminal of the pull-up transistor is connected with a first terminal of the pull-down transistor to together output a driving signal, and a second terminal of the pull-down transistor is connected to ground; and a control circuit connected with a control terminal of the pull-up transistor and/or the pull-down transistor respectively and configured to control the on or off switching of the pull-up transistor and/or the pull-down transistor so as to change the driving signal. The pull-up transistor and the pull-down transistor are not switched on at the same time under the control of the control circuit.

Abstract: A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

Abstract: Delay circuit includes: first to fourth transistors; capacitor; constant current source; and resistor. The first transistor has a gate connected to an input terminal, a source connected to the first power supply terminal, and a drain. The second transistor has a gate connected to an input terminal and the gate of the first transistor, a drain connected to the drain of the first transistor and the second terminal of the capacitor, and a source. The third transistor has a gate connected to a node between the drain of the first transistor, the drain of the second transistor, and the second terminal of the capacitor, a source connected to the second power supply terminal, and a drain. The fourth transistor has a gate connected to the node and the gate of the third transistor, a drain connected to the drain of the third transistor and an output terminal, and a source.

Abstract: A voltage generation circuit includes a plurality of rectification circuits configured to be selectively activated depending on a plurality of first control signals, and to generate an internal voltage according to respective reference voltages capable of being independently trimmed depending on a plurality of second control signals; a detection circuit configured to generate a detection signal by comparing a pre-detection signal, generated in each of the plurality of rectification circuits, and a reference signal; and a storage circuit configured to store a pre-select signal provided from an external system, and to output a stored signal to each of the plurality of rectification circuits as the plurality of second control signals.

Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Abstract: In one implementation, a matching network is provided comprising a pair of input terminals; a pair of output terminals; and at least two reactive components disposed between the pair of input terminals and the pair of output terminals. At least one of the reactive components comprises a coupled-inductor. In various implementations, the second reactive component can be a capacitor, and the capacitor can be at least partially realized using the parasitic capacitances of the environment. The matching network may be disposed in a capacitive wireless power transfer (WPT) system. In other implementations, inductors and coupled-inductors are further provided. In some implementations, for example, an inductor, such as but not limited to a coupled-inductor, may comprise a toroidal or semi-toroidal core comprising foil wire interleaved without notches.

Abstract: A propagation delay balance circuit includes a signal generating circuit, a path switching element, and a signal change detecting element. The signal generating circuit includes delay chains for outputting delay signals respectively. The path switching element has input terminals and output terminals. Each output terminal of the path switching element is electrically connected to the input terminal of each delay chain one-to-one, and input terminals of the path switching element are electrically connected one-to-one to the output terminals of the delay chains. The path switching element is controlled by the path switching controlling signal to change the one-to-one internal electrical connection between input terminals and output terminals of the path switching element. The signal change detecting element is electrically connected to the path switching element, and generates a path switching controlling signal according to delay signals of the path switching element.

Abstract: Methods, apparatus, and systems are disclosed to drive a transistor. An example apparatus includes a regulator including a first input terminal adapted to be coupled to a control terminal of a transistor, a first output terminal, and a second output terminal, a first stage including a first input terminal coupled to the first output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the transistor, and a second stage including an input terminal coupled to the second output terminal of the regulator, and an output terminal adapted to be coupled to the control terminal of the transistor.

Abstract: A phase shifter includes a first capacitor connected to a first line to which a first input signal is input, a second capacitor connected to a second line to which a second input signal having a first phase difference with respect to the first input signal is input, and a combining circuit that is connected to the first line and the second line and that outputs a combined signal having a phase determined depending on a first capacitance ratio between the first capacitor and the second capacitor.