Abstract: Methods and system for clock alignment are described. In an example, a timing device can distribute a clock signal to a line card via a trace of a backplane. The timing device can further send a pulse to the line card at a first time via the trace. The timing device can further receive a return pulse from the line card at a second time via the trace. The timing device can determine a time difference between the first time and the second time. The time difference can indicate a propagation delay associated with the line card and the trace. The timing device can send the time difference to the line card. The line card can adjust a phase delay offset of the line card using the time difference.

Abstract: Methods, systems, and devices for delay adjustment circuits are described. Amplifiers (e.g., differential amplifiers) may act like variable capacitors (e.g., due to the Miller-effect) to control delays of signals between buffer (e.g., re-driver) stages. The gains of the amplifiers may be adjusted by adjusting the currents through the amplifiers, which may change the apparent capacitances seen by the signal line (due to the Miller-effect). The capacitance of each amplifier may be the intrinsic capacitance of input transistors that make up the amplifier, or may be a discrete capacitor. In some examples, two differential stages may be inserted on a four-phase clocking system (e.g., one on 0 and 180 phases, the other on 90 and 270 phases), and may be controlled differentially to control phase-to-phase delay.

Abstract: Common-mode transient immunity circuit and modulation-demodulation circuit, common-mode transient immunity circuit is applied to connecting with modulation circuit or demodulation circuit, comprising first isolation circuit, common-mode bias circuit, reference circuit and comparison circuit. Common-mode bias circuit provides common-mode bias voltage for first isolation circuit; first isolation circuit transmits common-mode bias voltage to comparison circuit; reference circuit provides reference voltage for comparison circuit; comparison circuit compares common-mode bias voltage with reference voltage, when common-mode bias voltage is larger than reference voltage, comparison circuit outputs enable signal to modulation circuit or demodulation circuit, and modulation circuit is driven to stop outputting modulation signal or demodulation circuit is driven to stop receiving modulation signal.

Abstract: A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews.

Abstract: A potential generating circuit includes a first transistor and a second transistor. Potential at a substrate of the first transistor varies with a first parameter. The first parameter is any one of a supply voltage, an operating temperature, as well as a manufacturing process of the potential generating circuit. Potential at a substrate of the second transistor varies with the first parameter. A gate of the first transistor is connected to a drain of the first transistor. The substrate of the first transistor serves as a first output of the potential generating circuit. A gate of the second transistor is connected to a drain of the second transistor. The substrate of the second transistor serves as a second output of the potential generating circuit.

Abstract: An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.

Abstract: An injection locking oscillator (ILO) circuit includes; an injection circuit that receives input signals having a phase difference and provides injection signals respectively corresponding to the input signals based on a voltage level difference between each input signal and an oscillation signal at an output terminal, and a poly-phase signal output circuit that provides poly-phased signals having a phase difference between signals fixed to a defined phase difference upon receiving the injection signals from the input terminals.

Abstract: This application discloses a power supply and a power system. A first power supply is configured to set an output voltage of the first power supply to a plurality of voltage values. A second power supply is configured to send a plurality of first parameters to the first power supply, where the first parameters are used to identify power efficiency of the second power supply. The first power supply is further configured to obtain a plurality of second parameters, which are used to identify power efficiency of the first power supply. The first power supply is further configured to determine, based on the plurality of first parameters and the plurality of second parameters, maximum power efficiency of the power system and a voltage value corresponding to the maximum power efficiency.

Abstract: Rotary traveling wave oscillator-based (RTWO-based) frequency multipliers are provided herein. In certain embodiments, an RTWO-based frequency multiplier includes an RTWO that generates a plurality of clock signal phases of a first frequency, and an edge combiner that processes the clock signal phases to generate an output clock signal having a second frequency that is a multiple of the first frequency. The edge combiner can be implemented as a logic-based combining circuit that combines the clock signal phases from the RTWO. For example, the edge combiner can include parallel stacks of transistors operating on different clock signal phases, with the stacks selectively activating based on timing of the clock signal phases to generate the output clock signal of multiplied frequency.

Abstract: Systems and methods for supplying power at a medium voltage from an uninterruptible power supply (UPS) to a load without using a transformer are disclosed. The UPS includes an energy storage device, a single stage DC-DC converter or a two-stage DC-DC converter, and a multi-level inverter, each of which are electrically coupled to a common negative bus. The DC-DC converter may include two stages in a unidirectional or bidirectional configuration. One stage of the DC-DC converter uses a flying capacitor topology. The voltages across the capacitors of the flying capacitor topology are balanced and switching losses are minimized by fixed duty cycle operation. The DC-DC converter generates a high DC voltage from a low or high voltage energy storage device such as batteries and/or ultra-capacitors. The multi-level, neutral point, diode-clamped inverter converts the high DC voltage into a medium AC voltage using a space vector pulse width modulation (SVPWM) technique.

Abstract: An integrated circuit includes a signal output circuit configured to output a timing signal indicating first and second timings of respectively switching first and second switching devices, first and second hold circuits respectively configured to receive first and second voltages corresponding to temperatures of the first and second switching devices, hold the first and second voltages for first and second time periods, and output the received first and second voltages in response to the first and second time periods having elapsed, and first and second control circuits respectively configured to control switching of the first and second switching devices with first and second driving capabilities corresponding to the temperatures of the first and second switching devices, based on the first and second voltages outputted from the first and second hold circuits and first and second driving signals for driving the first and second switching device.

Abstract: A delay circuit includes the following: an input module, configured to receive a target input signal and output the target input signal to a first node, the target input signal being a rising edge signal or a falling edge signal of a pulse signal; an output module, configured to output a target output signal, the target output signal being a delayed signal of the target input signal; and a delay control module, connected to the input module through the first node, and connected to the output module through a second node. The delay control module includes at least one delay capacitor unit, and the delay control module is configured to control a connection between the at least one delay capacitor unit and the first node according to a rising edge delay duration or a falling edge delay duration.

Abstract: A control circuit and a delay circuit are provided. The control circuit includes a control unit and a feedback unit. The feedback unit is configured to output a feedback signal according to a voltage of the control unit and a reference voltage; a first terminal of the feedback unit is connected to a first terminal of the control unit, a second terminal of the feedback unit serves as an input terminal of the reference voltage, and an output terminal of the feedback unit is connected to a second terminal of the control unit. The control unit is configured to adjust a voltage of the second terminal of the control unit according to the feedback signal, so as to allow a current variation of the control unit with a first parameter to be within a first range.

Abstract: A delay line structure and a delay jitter correction method thereof are provided. The delay line structure comprises N delay units and N selectors. An output end of the N?1th delay unit is connected to a first input end of the N?1th selector and an input end of the Nth delay unit respectively, the N?1th selector inputs the N?1th selection signal, an output end of the Nth delay unit is connected to a first input end of the Nth selector, an output end of the Nth selector is connected to a second input end of the N?1th selector, and the Nth selector inputs the Nth selection signal. The time delay units and the selectors are stacked forwards according to the above-mentioned rule until the input ends of the first time delay units are connected with input signals and the output ends of the first selectors are connected with output signals.

Abstract: A jitter generator may include a duty cycle code generator that generates a duty cycle control signal and an input buffer that outputs a signal based on its duty cycle. The input buffer may be coupled to the duty cycle code generator and to a source of a clock signal. After receiving the clock signal, the input buffer outputs the clock signal having jitter relative to the clock signal received from the source. The jitter may be added at least in part by components of the input buffer offsetting different transitions of the clock signal according to the duty cycle. Jitter may be added when the duty cycle changes in response to changes in the duty cycle control signal, such as in response to number generator circuitry of the duty cycle code generator update its output number, in response to a mode change received from a controller, or the like.

Abstract: A power supply circuit portion for supplying power comprises a first power rail, a second power rail, first and second output terminals, an energy storage device connected in parallel with the first and second output terminals; and first and second switching portions. The power supply circuit portion has a first mode in which power is supplied to the first and second output terminals by the first and second power rails, and a second mode in which the first switching portion is arranged such that power is not supplied to the first and second output terminals and the second switching portion is arranged to disconnect the energy storage device from the first power rail.

Abstract: The present description concerns a comparator (1) of a first voltage (V+) and of a second voltage (V?), comprising first (100) and second (102) branches each comprising a same succession of alternated first (106) and second (108) gates in series between a node (104) and an output (1002; 1022) of the branch (100; 102), wherein: each branch starts with a first gate (106), each gate (106; 108) has a second node (114) receiving a bias voltage, the second node (114) of each first gate (106) of the first branch (100) and of each second gate (108) of the second branch (102) receives the first voltage (V+), the second node of the other gates receiving the second voltage (V?), and an order of arrival of the edges on the outputs (1002; 1022) of the branches determines a result of a comparison.

Abstract: A clock generator circuit includes: first to Nth nodes, where N is an even number equal to or greater than 2; and a parallel-to-serial conversion circuit suitable for parallel-to-serial converting signals of the first to Nth nodes to output a clock through an output node, wherein, in an activation section of the clock, the signals of even-numbered nodes among the first to Nth nodes have a first level, and the signals of odd-numbered nodes among the first to Nth nodes have a second level which is different from the first level, and wherein, in a deactivation section of the clock, the signals of the first to Nth nodes have the same level.

Abstract: A control circuit and a delay circuit are provided. The control circuit includes a control unit and a feedback unit. The feedback unit is configured to output a feedback signal according to a voltage of the control unit and a reference voltage; a first terminal of the feedback unit is connected to a first terminal of the control unit, a second terminal of the feedback unit serves as an input terminal of the reference voltage, and an output terminal of the feedback unit is connected to a second terminal of the control unit. The control unit is configured to adjust a voltage of the second terminal of the control unit according to the feedback signal, so as to allow a current variation of the control unit with a first parameter to be within a first range.

Abstract: A photovoltaic system with an inverter, at least one solar panel for providing electrical power, and electrical wiring for coupling electrical power from the at least one solar panel to the inverter. Also included is a transmitter for transmitting a messaging protocol along the electrical wiring, where the protocol includes a multibit wireline signal. Also included is circuitry for selectively connecting the electrical power from the at least one solar panel along the electrical wiring to the inverter in response to the messaging protocol.