Abstract: A frequency generator for generating a controlled signal having a controlled frequency uses a frequency ratio generator with an input; a frequency divider for dividing the controlled frequency by a frequency ratio signal to generate a divided signal having a divided frequency; a converter for generating an excitation signal having the divided frequency, the excitation signal exciting a resonator for generating a resonance signal having a resonance frequency; a frequency phase detector of a phase difference between the divided frequency and the resonance frequency; an inner loop filter for generating the frequency ratio signal and filtering the phase difference signal to prevent instability of two frequency ratio generator loops; an output configured for providing the frequency ratio signal based on a ratio between the controlled frequency and the resonance frequency; and a controlled oscillator circuit for generating the controlled signal based on comparison of the frequency ratio with a target ratio.

Abstract: A power supply system includes a first drive motor, a second drive motor, a first power line to which a first inverter and a first battery are connected, a second power line to which a second inverter and a second battery are connected, a voltage converter that converts a voltage between the first power line and the second power line, and an ECU that operates the first and second inverters and the voltage converter and controls charging and discharging of the first and second batteries. In a case where total required power is larger than first outputtable power of the first battery, the ECU discharges a shortage of power from the second battery to the second power line, wherein the shortage of power is obtained by excluding an amount that is output by the first battery from the total required power.

Abstract: The disclosure provides high voltage interlock circuit and detection method. The circuit comprises: a power module, a positive electrode of the power module being connected to one end of a current generating module; the current generating module, the other end of the current generating module being connected to a first terminal of a high voltage component module to inject a constant DC current into the high voltage component module; a first voltage dividing module, one end of the first voltage dividing module being connected to a second terminal of the high voltage component module, and the other end of the first voltage dividing module being connected to a negative electrode of the power module and a power ground; and a processing module to determine a fault of the high voltage component module based on a first voltage collected from the second terminal of the high voltage component module.

Abstract: A utility meter includes a real-time clock (RTC), a supercapacitor, a power supply, and a set of photodiodes. The RTC keeps time utilized for time stamps applicable to events that occur during alternating current (AC) power outages of the utility meter, and the supercapacitor powers the RTC. The power supply operates in an active mode responsive to an AC line voltage meeting a threshold and, when in the active mode, charges the supercapacitor to power the RTC. The set of photodiodes absorbs energy from ambient light and charges the supercapacitor to power the RTC. Thus, the supercapacitor is configured to be charged based on the power supply and based on the set of photodiodes.

Abstract: An output driving circuit may include a pull-up-pull-down driver connected to a pad, a level shifter operating based on a first power voltage and a second power voltage that is greater than the first power voltage, level shifting a data signal to generate a first control signal, and applying the first control signal to the pull-up-pull-down driver, and a driver control logic operating based on the first power voltage, generating a second control signal based on the data signal, and applying the second control signal to the pull-up-pull-down driver.

Abstract: A phase interpolating (PI) system includes: a phase-interpolating (PI) stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal, the PI stage being further configured to avoid a pull-up/pull-down (PUPD) short-circuit situation by using the multi-bit weighting signal and a logical inverse thereof (multi-bit weighting_bar signal); and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component; the capacitive component being tunable; and the capacitive component having a Miller effect configuration resulting in a reduced footprint of the amplifying stage.

Abstract: A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.

Abstract: An input buffer using a frequency dependent impedance circuit to compensate for nonlinearity in low frequency is shown. In a pseudo-differential architecture, a frequency-dependent impedance circuit is coupled between the drain of a positive input transistor of the flipped voltage follower and the drain of a negative input transistor of the flipped voltage follower. In a single-ended architecture, the frequency-dependent impedance circuit is coupled between the drain of an input transistor of the flipped voltage follower and an alternating current ground. The frequency-dependent impedance circuit includes a capacitor.

Abstract: A phased array system includes tunable delay elements having active delay element(s) and passive delay element(s). A second resolution by the passive delay element is smaller than a first resolution by the active delay element, and the resolution corresponds to delay applied to an input signal and has discrete steps for phase over which the delay element can be operated. For multiple sets of tunable delay elements, a calibration process sets, for one set of the delay elements, all but an n-th active delay element and the passive delay element to a first phase, and the n-th active delay element to a second phase. In a second set of the delay elements, all of the active delay elements are set to the first phase and the passive delay element is set to the second phase. A phase difference is detected and adjusted to meet a criterion between the two sets.

Abstract: A device includes a clock delay circuit configured to receive a reference clock signal and generate N delay clock signals, where N is a natural number greater than or equal to 2, by using the reference clock signal, and an output circuit configured to receive the N delay clock signals and output at least a portion of the delay clock signals from among the N delay clock signals as an output signal, wherein a phase delay of a delay clock signal that is output later in time from among the at least the portion of the delay clock signals is greater than or equal to a phase delay of a delay clock signal that is output earlier in time, and wherein a cycle of the output clock signal is longer than or equal to a cycle of the reference clock signal.

Abstract: A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.

Abstract: An output driving circuit includes a pull-down driver and a voltage stabilizer. The pull-down driver includes first, second, and third transistors connected in series between a pad and a ground node. The voltage stabilizer generates a stabilization voltage based on a voltage of the pad and a power voltage, and outputs the stabilization voltage to a control terminal of the second transistor.

Abstract: A semiconductor integrated circuit includes a first circuit and a second circuit. The first circuit is configured to divide a first pulse signal having a first duty cycle by N (where N is an integer of 2 or more), and output 2×N second pulse signals of which phases are different from each other. The first pulse signal is a pair of differential signals. The second circuit is configured to receive one or more selection signals and calculate a logical product of one of the one or more selection signals and two of the 2×N second pulse signals to generate a third pulse signal having a second duty cycle less than the first duty cycle.

Abstract: In one aspect, a clock monitor includes a frequency-to-voltage converter (FVC) configured to receive a clock signal and configured to generate a voltage signal in response to the clock signal received. The FVC includes a resistor and a switched capacitor (SC) circuit connected to the resistor to form a resister divider circuit. The switched capacitor circuit includes a capacitor. The clock monitor detects that a clock frequency is zero and/or the clock frequency is not within a frequency range.

Abstract: A quadrature clock generator includes a variable delay clock generator configured to receive a first clock and a third clock and output a second clock and a fourth clock in accordance with a control signal, wherein the first clock and the third clock are substantially the same but offset in timing by one half of the period; a quadrature phase error detector configured to receive the first clock, the second clock, the third clock, and the fourth clock and output a first phase detection signal and a second phase detection signal, wherein the first phase detection signal represents a relative timing between the first clock and the second clock and the second phase detection signal represents a relative timing between the second clock and the third clock; and an amplifier configured to amplify a difference between the first phase detection signal and the second phase detection signal into the control signal.

Abstract: An apparatus includes a phase modulator configured to modulate a phase of an incoming frequency-modulated signal based on a clock signal to generate a phase-modulated signal, where the clock signal is associated with a clock frequency. The apparatus also includes an etalon configured to receive the phase-modulated signal and generate an output signal based on the phase-modulated signal. The apparatus further includes a detector configured to identify amplitudes associated with a first harmonic of the clock frequency and a first subharmonic of the clock frequency in the output signal. In addition, the apparatus includes a decoder configured to recover information encoded in the incoming frequency-modulated signal based on instantaneous frequency deviations of the incoming frequency-modulated signal, where the instantaneous frequency deviations are identified based on relative amplitudes of the first harmonic and the first subharmonic.

Abstract: Aspects of the disclosure are directed to clock management. In accordance with one aspect, a clock management apparatus for built-in self-test (BIST) circuitry includes a plurality of local clock controllers; a plurality of clock generators coupled to the plurality of local clock controllers; a master clock controller coupled to the plurality of clock generators; an X-tolerant logical built-in self test (XLBIST) circuit coupled to the master clock controller; and a test access port (TAP) coupled to the XLBIST circuit.

Abstract: Various embodiments relate to digital demodulation for wireless power transmission. A wireless power transmitter includes a transmitter coil and a controller. The transmitter coil is configured to wirelessly couple to a receiver coil of a wireless power receiver to transfer power to the wireless power receiver responsive to a coil current applied to the transmitter coil. The wireless power receiver is configured to modulate at least one electrical condition of the wireless power receiver to modulate the coil current at the transmitter coil. The controller is configured to sample one or more electrical signals of the wireless power transmitter, and digitally demodulate the sampled one or more electrical signals to obtain a communication received from the wireless receiver responsive to the modulation of the at least one electrical condition of the wireless power receiver.

Abstract: A method for operating an IGBT includes determining a maximum stationary reverse bias required for operation of the IGBT, determining a first removal charge, the removal of which at the gate of the IGBT causes an electric field strength that enables the IGBT to accept the maximum stationary reverse bias during stationary blocking, determining a second removal charge, the removal of which at the gate causes an electric field strength that leads to a dynamic avalanche, and, when the IGBT is switched off, removing from the gate during a charge removal duration a removal charge that is greater than the first removal charge and smaller than the second removal charge.

Abstract: Power systems and methods of using the same to deliver power. A power system referenced herein can include a housing capable of attaching to a workstation, one or more cradles or mounting fixtures to receive at least one energy storage device, electronic circuitry to communicate status of the at least one energy storage device, state of charge of the at least one energy storage device, and/or overall health of the at least one energy storage device, and one or more electrical connectors to allow the at least one energy storage device to charge and/or discharge and communicate with the electronic circuitry, with said housing having an internal power supply and charge circuitry, said power supply capable of receiving input power from an external AC or DC power source; wherein the power system is configured to deliver power to the workstation.