Abstract: A data rebuilding method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: establishing a connection between the memory storage apparatus and a host system; storing a first data to a memory of the host system via the connection; detecting an error in the first data in the memory; and rebuilding a part of data in the first data in the memory according to the error.

Abstract: A data processing circuit and a fault-mitigating method are provided. In the method, multiple sub-sequences are divided from sequence data. A first sub-sequence of the sub-sequences is accessed from a memory for a multiply-accumulate (MAC) operation to obtain a first computed result. The MAC operation is performed on a second sub-sequence of the sub-sequences in the memory to obtain a second computed result. The first and the second computed results are combined, where the combined result of the first and the second computed results is related to the result of the MAC operation on the sequence data directly. Accordingly, the error rate could be reduced, so as to mitigate fault.

Abstract: A serial presence detect (SPD) device includes nonvolatile memory to store SPD information. Parity information suitable for single error correct and double error detect (SEC-DED) is also stored in association with the SPD information in the nonvolatile memory. The combination of SPD information and parity information is organized into codewords addressable at each memory location. During an initialization period occurring after a power on reset and before the SPD device is accepting I2C commands, the SPD device checks each memory location (codeword) for errors. Each error detected is counted to provide an indicator of device health. Before the initialization period expires, the SPD device writes a corrected codeword back to the nonvolatile memory.

Abstract: A method includes identifying an independent data object of a plurality of independent data objects for retrieval from dispersed storage network (DSN) memory. The method further includes determining a mapping of the plurality of independent data objects into a data matrix, wherein the mapping is in accordance with the dispersed storage error encoding function. The method further includes identifying, based on the mapping, an encoded data slice of the set of encoded data slices corresponding to the independent data object. The method further includes sending a retrieval request to a storage unit of the DSN memory regarding the encoded data slice. When the encoded data slice is received, the method further includes decoding the encoding data slice in accordance with the dispersed storage error encoding function and the mapping to reproduce the independent data object.

Abstract: A controller includes an interface and circuitry. The interface communicates with memory cells arranged in multiple address locations. Storage nodes holding storage values included in the memory cells are accessible using select transistors powered by an adjustable supply voltage. The circuitry reads data units protected by an Error Correction Code (ECC) from the memory cells and decode the ECC of the data units. Upon detecting, using the ECC, that a given data unit read from a given address location contains one or more errors, the circuitry logs an error event specifying at least a time of occurrence associated with the error event and the given address location. The circuitry identifies that the select transistors experience physical degradation due to aging, based on the times of occurrence and address locations logged in the error events, and adjusts the supply voltage provided to the select transistors to compensate for the physical degradation.

Abstract: Methods, systems, and devices for multiple bit error detection in scrub operations are described. A memory device may initiate a scrub operation on a set of rows of the memory device and determine whether to perform the scrub operation using a first error control mode associated with correcting single-bit errors or using a second error control mode associated with correcting single-bit errors and detecting multiple-bit errors. In a case that the memory device determines to perform the scrub operation using the second error control mode, the memory device may read data and first error control information from the set of rows and additional second error control information for a different partition of the memory device storing error control information. The memory device may then correct single-bit errors and detect multiple-bit errors based on the data, first error control information, and second error control information as part of the scrub operation.

Abstract: A master communication device of this communication system comprises: a generation unit that generates transmission data consisting of consecutive data to all slave communication devices following one header; and a transmission unit that transmits the transmission data generated by the generation unit at the fastest cycle, among communication cycles requested by the plurality of slave communication devices. Each of the plurality of slave communication devices of the communication system comprises: a storage unit that adds information indicating reliability to data received from the master communication device and stores the same; a comparison unit that compares the reliability of subsequently received data and the reliability of the data stored in the storage unit; and a selection unit that selects the data stored in the storage unit if the reliability of the data stored in the storage unit is higher than the reliability of the data subsequently received by the comparison unit.

Abstract: A system and method for detecting the preamble of a wireless packet is disclosed. The system utilizes one or more received fragments as inputs to a correlator, forming correlator content inside the correlator memory. After every sample from the received fragment is provided to the correlator, the correlator then compares the correlator content to a known pattern pre-programmed as a set of correlation coefficients. The correlation coefficients may not align with the correlator content because the symbol boundaries are not known a-priori. By cyclic rotation of the correlation coefficients relative to the correlator content, or cyclic rotation of the correlator content relative to the known correlation coefficients, a match with one or more preamble symbols may be found. This technique may be used to reduce power during the preamble detection process. Alternatively, this technique can also be used for antenna diversity, multi PHY and multichannel applications.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller and an operating method of the memory system. According to embodiments of the present disclosure, the memory system may receive, from an outside of the memory system, a read command, execute a defense code on the data when a failure occurs during an operation of reading data from the memory device in response to the read command, and transmit defense code information, which is information related to the execution of the defense code for data, to the outside of the memory system.

Abstract: In an example, a scan flip-flop includes a first transistor and a second transistor coupled to a data input. The scan flip-flop includes a third transistor coupled to a clock input and a fourth transistor coupled to an inverse clock input. The scan flip-flop includes a fifth transistor coupled to a scan enable input and the first transistor, and includes a sixth transistor coupled to an inverse scan enable input and the second transistor. The scan flip-flop includes an input multiplexer that includes a seventh transistor and eighth transistor coupled to the scan data input, a ninth transistor coupled to the scan enable input, and a tenth transistor coupled to the inverse scan enable input. The input multiplexer includes a first diode-connected transistor coupled between a first voltage rail and the seventh transistor, and includes a second diode-connected transistor coupled between a second voltage rail and the eighth transistor.

Abstract: A memory device comprising a memory array including memory cells to store memory data, error correcting code (ECC) circuitry configured to generate ECC data and use the ECC data to detect errors in the memory data, and an ECC circuitry checker. The ECC circuitry checker is configured to substitute the ECC data with check ECC data, compare an output of the ECC circuitry to an expected output when the substituted check ECC data is applied to the ECC circuitry, and generate an alert when the comparing indicates an error in the ECC circuitry.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with a data inversion and unidirectional error detection are described. An apparatus for data inversion and unidirectional error detection can include a memory device and a processing device communicatively coupled to the memory device. The processing device can be configured to encode a plurality of binary data bits in an information word, encode the information word using a unidirectional error detecting code, write the encoded information word to the memory device, read the encoded information word from the memory device, and detect an error in the information word using a unidirectional error detecting code. The encoding can include inverting the plurality of binary data bits and adding an inversion data bit to the information word.

Abstract: Systems and methods are disclosed for implementing a low latency decoder. In certain embodiments, an apparatus may comprise decoder configured decode a codeword of bits, including: a variable node processor configured to provide a plurality of variable-to-check (v2c) message vectors to the edge combiner in parallel, the plurality of v2c message vectors including estimates for a selected set of bits of the codeword; the edge combiner configured to generate a plurality of output message vectors for a plurality of check node vectors based on the plurality of v2c message vectors, and provide the plurality of output message vectors to the plurality of check node vectors simultaneously; a check node processor configured to update the plurality of check node vectors based on the plurality of output message vectors; and a convergence checker circuit configured to detect a valid code word based on bit value estimates from the variable node processor.

Abstract: Embodiments of the present disclosure provide a level-sensitive register unit, including: a data latch for receiving data; a flip-flop including a first latch and a second latch, wherein an output of the data latch is coupled to an input of the first latch of the flip-flop; a first clock signal coupled to the data latch; and a second clock signal, wherein the second latch of the flip-flop is clocked by the second clock signal, and wherein the first latch of the flip-flop is clocked by an inverse of the second clock signal.

Abstract: A redundant multiport memory for vehicle applications can have different ports coupled to different hosts that are configured to provide advanced driver assistance system (ADAS) for the vehicle. Different multiport memory devices can provide primary or secondary storage of data for the hosts. At least one of the hosts can perform a functionality check on at least one of the multiport memory devices and make use of a second multiport memory device to which it is coupled if a first multiport memory device to which it is coupled fails the check.

Abstract: The devices, methods, and apparatuses of the present disclosure address a lack of parallelism in a typical approach by eliminating the static mapping of the two or more low-density parity check (LDPC) engines to a plurality of flash controllers. The devices, methods, and apparatuses of the present disclosure include a dynamic LDPC mapping to the plurality of flash controllers.

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, identifying a block family comprising a plurality of blocks of the memory device. The operations performed by the processing device further include associating the block family with a threshold voltage offset. The operations performed by the processing device further include computing an adjustment value of the threshold voltage offset, wherein the adjustment value reflects a time period that has elapsed since a triggering event and a temperature of a memory component carrying one or more blocks of the plurality of blocks.

Abstract: An information handling system includes a memory module, a memory controller coupled to the memory controller by a memory bus, and an expansion memory device coupled to the memory controller by a data communication interface. The memory controller receives user data, calculates error correction code (ECC) data for the user data, determines metadata related to the user data, writes the user data and the ECC data to the memory module via the memory bus, and stores the metadata to the expansion memory device with a transaction on the data communication interface.

Abstract: An operating method of a memory system includes preprogramming multi-page data of a memory controller to a nonvolatile memory device, generating a state group code based on multi-bit data of the multi-page data, and each state group data of the state group code having less number of bits than corresponding multi-bit data, detecting sudden power-off occurring after the preprogramming, backing up, in response to the detecting of the sudden power-off occurring, the state group code to the nonvolatile memory device, recovering, after power is recovered from the sudden power-off, the multi-page data from the nonvolatile memory device, based on the state group code, reprogramming the multi-page data to the nonvolatile memory device, and reprogramming, in response to the detecting of the sudden power-off not occurring, the multi-page data of the memory controller to the nonvolatile memory device.