Abstract: An information handling system includes a memory module, a memory controller coupled to the memory controller by a memory bus, and an expansion memory device coupled to the memory controller by a data communication interface. The memory controller receives user data, calculates error correction code (ECC) data for the user data, determines metadata related to the user data, writes the user data and the ECC data to the memory module via the memory bus, and stores the metadata to the expansion memory device with a transaction on the data communication interface.

Abstract: An operating method of a memory system includes preprogramming multi-page data of a memory controller to a nonvolatile memory device, generating a state group code based on multi-bit data of the multi-page data, and each state group data of the state group code having less number of bits than corresponding multi-bit data, detecting sudden power-off occurring after the preprogramming, backing up, in response to the detecting of the sudden power-off occurring, the state group code to the nonvolatile memory device, recovering, after power is recovered from the sudden power-off, the multi-page data from the nonvolatile memory device, based on the state group code, reprogramming the multi-page data to the nonvolatile memory device, and reprogramming, in response to the detecting of the sudden power-off not occurring, the multi-page data of the memory controller to the nonvolatile memory device.

Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

Abstract: A method begins by a processing module concurrently receiving a first data stream and a second data stream for transmission to a receiving entity. The method continues with the processing module dividing each of the first and second data streams to produce a first plurality of data blocks corresponding to the first data stream and a second plurality of data blocks corresponding to the second data stream, where data blocks of the first plurality of data blocks are time aligned with data blocks of the second plurality of data blocks. The method continues with the processing module creating a data matrix from the first and second plurality of data blocks and generating a coded matrix from the data matrix and an encoding matrix. The method continues with the processing module outputting a plurality of pairs of coded values of the coded matrix to the receiving entity.

Abstract: A processing system of a storage network operates by: generating a request for a plurality of system registry files; receiving the plurality of system registry files via a network; generating a verification indicator based on an integrity check of the plurality of system registry files versus system registry integrity data corresponding to the plurality of system registry files; and storing the system registry files in memory when the verification indicator indicates that verification was successful.

Abstract: A data encoding device suitable for encoding a plurality of LDPC codes is disclosed including an input interface and an output interface, and a first circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of a first multiplexer circuit, a second circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit, a third circuit for encoding quasi-cyclic LDPC code, connected at an input to the output of the first multiplexer circuit and at an output to the input of a second multiplexer circuit.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: The present disclosure relates to low-density parity-check (LDPC) encoding methods and apparatus. One example method includes encoding k information bits by using a submatrix of ((n?k)/Z+j) rows and (n/Z+j) columns at an upper left corner of a check matrix H based on a first transmission code rate R satisfying R=k/(n+j×Z), obtaining a first codeword including the k information bits and (n?k+j×Z) redundant bits, and sending the first codeword to a receive end.

Abstract: A system includes a memory device having groups of managed units and a processing device coupled to the memory device. The processing device, during power on of the memory device, causes a read operation to be performed at a subset of a group of managed units and determines a bit error rate related to data read from the subset of the group of managed units. The bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states. In response to the bit error rate satisfying a threshold criterion, the processing device causes a rewrite of the data stored at the group of managed units.

Abstract: A multicycle path circuit capable of operating at a functional mode and an at-speed test mode. The multicycle path circuit includes an on-chip controller configured to receive an on-chip clock signal and modulate the on-chip clock signal to provide a first clock signal to a first circuit and a second clock signal to a second circuit. The first clock signal and the second clock signal are in a multicycle phase relationship. The on-chip controller is configured to ensure the clock paths to and from the second circuit to be the same for the functional mode and the at-speed test mode and therefore to avoid hold and setup timing conflict between these modes.

Abstract: Example embodiments are disclosed of systems and methods for predicting failure probabilities of future product tests of a testing sequence based on outcomes of prior tests. Predictions are made by a machine-learning-based model (MLM) trained with a set of test-result sequence records (TRSRs) including test values and pass/fail indicators (PRIs) of completed tests. Within training epochs over the set, iterations are carried out over each TRSR. Each iteration involves sub-iterations carried out successively over test results of the TRSR. Each sub-iteration involves (i) inputting to the MLM values of a given test and those of tests earlier in the sequence while masking those later in the sequence, (ii) computing probabilities of test failures for the masked tests found later in the sequence than the given test, and (iii) applying the PFIs of test results later in the sequence than the given test as ground-truths to update parameters of the MLM.

Abstract: A method of operating a memory controller includes: collecting hard decision information based on data read from memory cells of a monitoring unit using a normal read level; collecting soft decision information based on data read from the monitoring unit using one or more offset read levels that are different from the normal read level; storing first strong error information determined based on the hard decision information and the soft decision information in a memory in the memory controller; and updating second strong error information determined for the monitoring unit in the memory after the first strong error information is stored. The second strong error information is used to correct an error in data read in response to a read request from a host.

Abstract: Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.

Abstract: A low-density parity-check (LDPC) code encoding method and a communication apparatus are described that provide increased redundant bits through retransmission in an IR-HARQ mechanism, so as to decrease a channel coding rate, and improve decoding performance of an LDPC code. A check matrix of the LDPC code is used as a basic matrix, and the basic matrix is extended to obtain a mother matrix compatible with a plurality of code rates. During LDPC encoding, a transmit device reads, from the mother matrix, a check matrix corresponding to a required code rate, and performs LDPC encoding on an information bit sequence based on the read check matrix. LDPC encoding is performed on the information bit sequence by using check matrices of different sizes, to obtain different quantities of redundant bits.

Abstract: Technologies and techniques for monitoring the reliability of an electronic system having one or more electronic components. A transmission quality of signals transmitted to or from the electronic system over a wired electrical signal transmission path are measured at different measurement times and according to a predetermined transmission quality measure. For each of the measurement times, the associated measured transmission quality is compared with a respective associated transmission quality reference value previously determined according to the transmission quality measure. A value of a reliability indicator associated with the respective measurement time is determined in dependence on the result of the associated comparison.

Abstract: A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.

Abstract: Embodiments herein provide a method for predicting iterations for decoding an encoded data at an electronic device. The method includes: receiving, by the electronic device, the encoded data; detecting, by the electronic device, signal parameters associated with the encoded data; predicting, by the electronic device, one of a cyclic redundancy check (CRC) failure, CRC success, and a CRC uncertainty in iterations for decoding the encoded data based on the signal parameters using a Neural Network (NN) model.

Abstract: A system for transmission of quantum information for quantum error correction includes an ancilla qubit chip including a plurality of ancilla qubits, and a data qubit chip spaced apart from the ancilla qubit chip, the data qubit chip including a plurality of data qubits. The system includes an interposer coupled to the ancilla qubit chip and the data qubit chip, the interposer including a dielectric material and a plurality of superconducting structures formed in the dielectric material. The superconducting structures enable transmission of quantum information between the plurality of data qubits on the data qubit chip and the plurality of ancilla qubits on the ancilla qubit chip via virtual photons for quantum error correction.

Abstract: A method may include, and/or a device may be configured for: receiving, from a transmitting device, a signal corresponding to input bits; performing demodulation based on the signal to determine values corresponding to the input bits; identifying a number of the input bits based on the signal; identifying a base matrix and a lifting size based on the number of the input bits; identifying a parity check matrix based on the base matrix; determining a number of layers based on the lifting size and a number of the values; determining an order of layers for low density parity check (LDPC) decoding based on the number of layers; and performing the LDPC decoding to determine the input bits based on the values, the parity check matrix, and the order of layers.

Abstract: This application discloses a fault tolerant computation method and device for a quantum Clifford circuit with reduced resource requirement. The method includes decomposing a quantum Clifford circuit into s logic Clifford circuits and preparing auxiliary quantum states corresponding to the s logic Clifford circuits. For each logic Clifford circuit, the method further includes teleporting an input quantum state corresponding to the logic Clifford circuit to an auxiliary qubit, processing a quantum state obtained after the teleportation by the logic Clifford circuit to obtain a corresponding output quantum state; measuring a corresponding error symptom based on the input quantum state and the auxiliary quantum state; and performing error correction on the output quantum state according to the error symptom to obtain an error-corrected output quantum state.