Abstract: The subject technology provides for scanning blocks of a flash memory device for erased pages. A first codeword read from a page of a block in a flash memory device is received and provided to a first decoder for decoding. In response to receiving a first success indicator from the first decoder indicating that the first codeword was successfully decoded, first decoded data is provided from the first decoder to a second decoder for verification of the first decoded data. In response to receiving a first failure indicator from the second decoder indicating that the first decoded data was not verified, the page of the block is identified as being in an erased state based on the first success indicator received from the first decoder and the first failure indicator received from the second decoder.

Abstract: Disclosed are systems, methods, and software for generating spatially-coupled low-density parity-check (SC-LDPC) codes. A method for generating SC-LDPC codes includes generating one or more quasi-cyclic low-density parity-check (QC-LDPC) codes, and also includes assigning at least one of the generated one or more QC-LDPC codes as one or more template codes. The method further includes copying at least a portion of the one or more template codes to introduce irregularity. The method also includes shifting one or more template codes on a sub-block basis to generate at least one SC-LDPC code. As compared to known LDPC code generation modalities, the disclosed invention provides a simplified technique for implementation in streamlined hardware which has more general applicability across both present, and anticipated, communication systems, including those adapted for use with optical communications, wireless communications, and 5G as well as future 6G.

Abstract: A memory controller includes an error correction code (ECC) engine and an error managing circuit. The ECC engine is configured to, during a read operation, perform an ECC decoding on a read codeword set to generate a first and second syndrome associated with a correctable error in a user data set included in the read codeword set, correct the correctable error based on the first syndrome and the second syndrome, and provide the second syndrome to the error managing circuit. The error managing circuit is configured to accumulate second syndromes associated with a plurality of correctable errors and obtained through a plurality of read operations as a plurality of second syndromes, store the plurality of second syndromes, compare the plurality of second syndromes with an error pattern set, and predict an occurrence of an uncorrectable error associated with the correctable error in a memory region based on the comparison.

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.

Abstract: Methods, systems, and devices for error caching techniques for improved error correction in a memory device are described. An apparatus, such as a memory device, may use an error cache to store indications of memory cells identified as defective and may augment an error correction procedure using the stored indications. If one or more errors are detected in data read from the memory array, the apparatus may check the error cache, and if a bit of the data is indicated as being associated with a defective cell, the bit may be inverted. After such inversion, the data may be checked for errors again. If the inversion corrects an error, the resulting data may be error-free or may include a reduced quantity of errors that may be correctable using an error correction scheme.

Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

Abstract: A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

Abstract: A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.

Abstract: Techniques for using stark tone pulses to mitigate cross-resonance collision in qubits are presented. A tone management component can control application of pulses to qubits by a tone generator component to mitigate undesirable frequency collisions between qubits. The tone generator component (TGC) can apply an off-resonant tone pulse to a qubit during a gate to induce a stark shift. TGC can apply a cross-resonance tone pulse to a control qubit at a frequency associated with the qubit, wherein the frequency can be stark shifted based on the off-resonant tone pulse. The qubit can be a target qubit, the control qubit itself, or a spectator qubit that can be coupled to the target qubit or the control qubit. The gate can be a cross-resonance gate, a two-qubit gate, or a measurement gate that can utilize an echo sequence, a target rotary, or active cancellation.

Abstract: Disclosed are a method and an apparatus for high-speed decoding of a linear code on the basis of a soft decision. The method for high-speed decoding of a linear code on the basis of a soft decision may comprise the steps of: obtaining an alignment signal by aligning received signals in order of magnitude; obtaining a hard decision signal by making a hard decision on the alignment signal; obtaining a higher-level signal corresponding to most reliable bases (MRB) from the hard decision signal; obtaining a permuted and corrected codeword candidate by using an error vector according to a current order and the higher signal; calculating a cost for the current order by using a cost function; determining the permuted and corrected codeword candidate as a permuted and corrected codeword according to a result of comparing the calculated cost and the minimum cost; and determining a predefined high-speed condition.

Abstract: An encoding method includes, when a first code rate K/Nmax is less than or equal to a code rate threshold Rt, reading a first matrix from a preset code table based on a second matrix. The second matrix includes a matrix that is read from the preset code table and that corresponds to a maximum supported code length Nmax and Rt, where K is an integer and N is an integer. The method also includes reading K rows and (N?K) columns starting from a preset first location in the first matrix to obtain a third matrix. The method further includes adding a unit matrix with K rows and K columns to a left side of the third matrix to obtain a generator matrix of an (N, K) linear block code. K rows and (Nmax?Nmax×Rt) columns of the second matrix in a first direction are consistent with K rows and (Nmax?Nmax×Rt) columns of the first matrix in a second direction.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.

Abstract: Various example embodiments for supporting forward error correction (FEC) in a communication system are presented. Various example embodiments for supporting FEC in a communication system may include the selection of a FEC setting for a communication channel from a transmitter to a receiver, e.g., the selection of a FEC setting for a communication channel, the selection of a FEC setting for a data burst sent over a communication channel, the selection of a FEC setting for a portion of a data burst sent over a communication channel, switching between FEC settings for different portions of a data burst over a communication channel, or the like, as well as various combinations thereof.

Abstract: Embodiments disclose an encoding method and a communications device. The method includes: obtaining and encoding a to-be-encoded information bit sequence based on a binary vector P1 of a first code, to obtain and output an encoded bit sequence, where P1 is determined based on a binary vector P2 of a second code and a binary vector P3 of a third code, P1, P2, and P3 indicate an information bit and a frozen bit of the first code, the second code and the third code respectively, a code length of the first code, the second code and the third code is n1, n2 and n3 respectively, a quantity of information bits of the first code, the second code and the third code is k1, k2 and k3 respectively, n1=n2*n3, and k1=k2*k3. Therefore, parallel decoding can be performed, helping reduce a decoding delay.

Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

Abstract: A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

Abstract: Apparatus for quantum error correction is disclosed. The apparatus includes an array of processing cores, each processing core comprising: a processor on a first chip; and a processor cache on the first chip; and a bus for interconnecting neighbouring processing cores in the array of processing cores; wherein each processing core includes: control code which, when executed by the processor, causes the processor to access a processor cache of at least one neighbouring processing core.

Abstract: An integrated circuit includes a first set of inverters configured to receive a first set of check bits, and to generate a second set of check bits, a first memory cell array including a first portion of memory cells configured to store a first set of data, and a second portion of memory cells configured to store the second set of check bits, a second set of inverters to receive a third set of check bits, and to generate a fourth set of check bits, and an error correction code decoder configured to detect or correct an error in a second set of data or the fourth set of check bits thereby generating a set of output data and a been-attacked signal. The second set of data corresponds to the first set of data. The been-attacked signal indicates a reset attack by a user.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n?1 data portions of a first unit that are included in n?1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n?1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n?1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.