Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

Abstract: Devices and methods for enhancing forward error correction techniques for communications using chirp spread spectrum are disclosed. Systems, devices, and methods for error correction coding and decoding are described. On the coding side, K bits of data are sequentially loaded into an M bit by N bit (M×N) matrix in a first direction as Q sequences of D bits, each D bit row of data in the M×N matrix is coded with an error correction code to generate an M bit row of coded data, each Q bit column in the M×N matrix is coded with the error correction code to generate N bits of coded data, N sequences of M bits are sequentially unloaded from the M×N matrix in a second direction, and a chirp signal is generated having a plurality of chirps.

Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.

Abstract: A computer-implemented method includes receiving a neural network model that includes a tensor operation, dividing the tensor operation into a set of sub-operations, and generating instructions for performing a plurality of sub-operations of the set of sub-operations on respective computing engines of a plurality of computing engines on a same integrated circuit device or on different integrated circuit devices. Each sub-operation of the set of sub-operations generates a portion of a final output of the tensor operation. An inference is made based on a result of a sub-operation of the plurality of sub-operations, or based on results of the plurality of sub-operations.

Abstract: This disclosure discloses a fault tolerant and error correction decoding method and apparatus for a quantum circuit, and a chip. This disclosure relates to the field of artificial intelligence (AI) and quantum technologies. The method includes: obtaining actual error syndrome information of a quantum circuit by performing a noisy error syndrome measurement on the quantum circuit by using a quantum error correction (QEC) code; decoding the actual error syndrome information to obtain a logic error class and perfect error syndrome information that correspond to the actual error syndrome information; and determining error result information of the quantum circuit based on the logic error class and the perfect error syndrome information, the error result information being indicative of a data qubit in which an error occurs in the quantum circuit and a corresponding error class.

Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.

Abstract: A request is received to program host data to a memory device of a memory sub-system. The host data is associated with a logical address. A redundancy factor that corresponds to the logical address associated with the host data is obtained. A first physical address associated with a first set of cells of the memory device and a second physical address associated with a second set of cells of the memory device are determined based on the redundancy factor. The first set of memory cells is to store the host data and the second set of memory cells is to store redundancy metadata associated with the host data. The host data is programmed to the first set of memory cells. The redundancy metadata associated with the host data is programmed to the second set of memory cells.

Abstract: A controller includes a processing circuit that writes each of a plurality of data fragments each including a part of data to be written in one memory chip of a plurality of memory chips each having an error correction function, and reads the data fragments corresponding to the data to be read from the memory chips, a first encoder that encodes the data to be written with an erasure correction code such that each of the data fragments includes a parity, and a first decoder that performs erasure correction by use of a part of the data fragments corresponding to the data to be read according to a completion status or success or failure of error correction on a corresponding part of the data fragments in each of the memory chips, the completion status or the success or failure of the error correction being acquired via a signal line.

Abstract: Methods, systems and apparatus, including computer programs encoded on computer storage medium, for predicting a likelihood of a future computer memory failure. In one aspect training data inputs are obtained, where each training data input includes correctable memory error data that describes correctable errors that occurred in a computer memory and data indicating whether the correctable errors produced a failure of the computer memory. For each training data input, image representations of the correctable memory error data included in the training data input are generated. The image representations are processed using a machine learning model to output an estimated likelihood of a future failure of the computer memory. A difference between the estimated likelihood of the future failure of the computer memory and the data indicating whether the correctable errors produced a failure of the computer memory is computed. Values of model parameters are updated using the computed difference.

Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.

Abstract: A data sampling circuit includes a frequency dividing circuit, a sampling circuit and a selection circuit. The frequency dividing circuit is configured to receive a first data sampling signal, and perform frequency dividing processing on the first data sampling signal to obtain multiple second data sampling signals associated with respective phases; the sampling circuit is configured to receive the multiple second data sampling signals and a first data signal, and sample the first data signal according to the multiple second data sampling signals to obtain multiple second data signals associated with respective phases; and the selection circuit is configured to receive preamble information and mode register set (MRS) information, and select among the multiple second data sampling signals and the plurality of second data signals according to the preamble information and the MRS information to obtain a target data sampling signal and a target data signal respectively.

Abstract: A method and a device for correcting quantum state information are disclosed. A decoder receives information identifying syndrome values for a plurality of entangled qubit states represented by a graph state with a respective edge of the graph state corresponding to a respective qubit state of the plurality of entangled qubit states. The decoder repeats identifying one or more clusters of qubit states and/or syndrome states in the graph state until all of the one or more identified clusters are determined to be valid while increasing a size of a respective cluster each time the identifying operation is performed. The decoder reconstructs one or more qubit states and/or syndrome states for respective clusters; and stores information identifying the one or more reconstructed qubit states and/or syndrome states.

Abstract: Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit (620) searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) (630) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.

Abstract: In one embodiment, a method includes transmitting pulse power on two wire pairs, the pulse power comprising a plurality of high voltage pulses with the high voltage pulses on the wire pairs offset between the wire pairs to provide continuous power, performing low voltage fault detection on each of the wire pairs between the high voltage pulses, and transmitting data on at least one of the wire pairs during transmittal of the high voltage pulses. Data transmittal is suspended during the low voltage fault detection.

Abstract: According to some embodiments, a method for use in a wireless transmitter of a wireless communication network comprises encoding information bits using a purity check matrix (PCM) and transmitting the encoded information bits to a wireless receiver. The parity check matrix (PCM) is optimized according to two or more approximate cycle extrinsic message degree (ACE) constraints. In some embodiments, a first portion of the PCM is optimized according to a first ACE constraint and a second portion of the PCM is optimized according to a second ACE constraint.

Abstract: The present application discloses a coding pattern, coding and reading methods for the same, a calibration board, and a calibration method. In the present application, the coding pattern comprises four positioning blocks, wherein three of the positioning blocks are located at three corner portions of the coding pattern, and the remaining positioning block only contacts one edge of the coding pattern, thereby forming an asymmetrical distribution configuration of the four positioning blocks. The invention can replace a two-dimensional code standard in the related art, saving the licensing and manufacturing costs of using two-dimensional code generation software in the related art, and is not subject to usage restrictions of the two-dimensional code generation software in the related art.

Abstract: Provided are a processing method and device for quasi-cyclic low density parity check (LDPC) coding. The processing method for LDPC coding includes: determining, according to a data feature of an information bit sequence to be encoded, a processing strategy for the quasi-cyclic LDPC coding according to a data feature of an information bit sequence to be encoded; and performing, according to the processing strategy and based on a base matrix and a lifting size, the quasi-cyclic LDPC coding and rate matching output on the information bit sequence according to the processing strategy, a base matrix and a lifting value. This technical solution is able to improve adaptability and flexibility of the quasi-cyclic LDPC coding.

Abstract: In an embodiment, a method includes measuring a first number of control qubits in a quantum algorithm, wherein a quantum circuit representation of the quantum algorithm includes a multiple-controlled-NOT gate. In an embodiment, a method includes measuring a second number of ancilla qubits in a quantum computer. In an embodiment, a method includes comparing the first number and the second number to determine an optimum compilation method for a quantum circuit. In an embodiment, a method includes compiling, in response to the comparison determining the second number is greater than one and less than the difference of the first number and 2, a quantum circuit from the quantum algorithm using a hybrid method.

Abstract: For respective positive integer value n, performing an outer and inner procedures, for states sufficiently representing coherent-error in a quantum system. Inner procedure creates copies state entangling n-qudits using randomized compiling, and obtains measurements of n-qudits in a basis corresponding to f-states. An outcome bit string forms for the state from measurement. The outer procedure and the forming string repeats, obtaining outcome bit strings for each state. Error-rate is determined for each state using the outcome bit strings for the respective value n. The outer procedure through determining error-rate repeats for different n drawn from positive-integers, determines error-rate for each state for respective values n. For state-S, error-rate fits for each respective value-n of the state to a corresponding quadratic function, the error-rate as dependent variable and n as independent variable.

Abstract: A system and method for polar code coding with information bits placed in particular bit indexes are disclosed herein. In one embodiment, a method for channel coding includes: associating, by a polar code encoder, a first bit sequence with first bit indexes of a polar code input; associating, by the polar code encoder, a second bit sequence with second bit indexes, wherein the first bit indexes have a higher reliability than the second bit indexes; and encoding, by the polar code encoder, both the first bit sequence and the second bit sequence using a generator matrix to generate encoded bits.