Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.

Abstract: A method and system to reorganize a storage structure by generating correlation data that represents relationships between storage blocks of a storage structure, generating a block allocation scheme for the storage structure, determining a block reorganization operation, performing the block reorganization operation, and updating a virtual map. In certain embodiments, the system may include multiple host computers, a data storage subsystem, and multiple storage structures. The storage structures may include a hard disk, an array of hard disks, an IBM TotalStorage™ system, and a hierarchical storage system with RAID.

Abstract: A method and system for processing data. In one embodiment, the method includes receiving a first store and receiving a second store subsequent to the first store. The method also includes generating a pointer that points to the last store that needs to retire before the second store retires, where the pointer is associated with the second store, and the last store that needs to retire is the first store.

Abstract: To ensure efficient access to a memory whose writing process is slow. There is provided a storage device for caching data read from a main memory and data to be written in the main memory, comprises a cache memory having a plurality of cache segments, one or more cache segments holding data matching with data in the main memory being set in a protected state to protect the cache segments from a rewrite state, an upper limit of a number of the one or more cache segments being a predetermined reference number; and a cache controller that, in accordance with a write cache miss, allocates a cache segment selected from those cache segments which are not in the protected state to cache write data and writes the write data in the selected cache segment.

Abstract: A system for providing improved cluster operation performance comprises a storage system and a cluster system communicatively coupled to the storage system. The cluster system comprises an active node and a plurality of passive nodes. The active node comprises a storage system interface engine and at least one initiator engine and each of the plurality of passive nodes comprises a storage system interface engine and at least one initiator engine. The storage system interface engine of the active node is configured to coordinate communication between the cluster system and the storage system, and simultaneously communicate an operation request from each of the plurality of passive nodes of the cluster system to the storage system.

Abstract: The storage control apparatus of the present invention saves a table for managing a virtual volume in a pool and keeps the state of the table in the latest state. A first dynamic mapping table (DMT) that manages a first virtual volume is saved in a first pool. Upon receipt of a write command relating to an unused virtual slot from a write command issuing device, a first virtual volume control unit assigns an unused real slot in the first pool to the virtual slot and updates the first DMT. The first virtual volume control unit discriminates the validity of the received data and, in cases where “0” data are received, releases the assigned real slot, updates the first DMT once again, and discards the received data. In cases where the received data are valid data, de-staging is performed following a DMT update.

Abstract: In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a first instruction, including forming an address responsive to one or more operands of the first instruction. The system is configured to push a first cache block that is hit by the first address in the first cache to a target location within the cache hierarchy or the main memory system, wherein the target location is unspecified in a definition of the first instruction within an instruction set architecture implemented by the first processor, and wherein the target location is implementation-dependent.

Abstract: A plurality of disk drives in a disk drive array are synchronized. A synchronization signal is generated at a master disk drive. The synchronization signal is encoded as a radio frequency signal for transmission over a radio frequency network in communication with the plurality of disk drives. The transmitted radio frequency signal is received at a slave disk drive and decoded to recover the synchronization signal. Rotation of a disk in the slave disk drive is synchronized with rotation of a disk in the master disk drive based on the recovered synchronization signal.

Abstract: A plurality of processors in a multiprocessor circuit is electrically connected to a plurality of independently addressable memory banks via a connection circuit. The connection circuit is arranged to forward addresses from a combination of the processors to addressing inputs of memory banks selected by the addresses. The connection circuit provides for a conflict resolution scheme wherein at least one of the processors is associated with one of the memory banks as an associated processor. The connection circuit guarantees the associated processor a higher minimum guaranteed access frequency to the associated memory banks than to non-associated memory banks. A defragmenter detects data associated with a task running on the associated processor that is stored on one of the memory banks and moves the data to the associated memory banks during execution of the task.

Abstract: It is not uncommon for two or more wireless-enabled devices to spend most of their time in close proximity to one another. For example, a person may routinely carry a personal digital assistant (PDA) and a portable digital audio/video player, or a cellphone and a PDA, or a smartphone and a gaming device. When it is desirable to increase the memory storage capacity of a first such device, it may be possible to use memory on one or more of the other devices to temporarily store data from the first device.

Abstract: A memory controller sequentially holds access requests including access addresses. A semiconductor memory includes a plurality of banks each having a plurality of pages. The memory controller decides page hit/page miss of the bank corresponding to each of the held access addresses. Further, the memory controller outputs an all-banks precharge command for performing a precharge operation of all the banks when deciding, based on an analysis of the successive access addresses, that outputting the all-banks precharge command results in improvement in access efficiency. It is possible to precharge the plural banks only by supplying the all-banks precharge command once, and therefore, in a case where the number of empty cycles for the insertion of a command is small, it is possible to supply the command efficiently to the semiconductor memory according to the states of the banks.

Abstract: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. A type of memory block is selected to receive additional data of a file that depends upon the types of blocks into which data of the file have already been written. Blocks containing data are selected for reclaiming any unused capacity therefrom by a process that selects blocks in order starting with those containing the least amount of valid data.

Abstract: Data files are assigned addresses within one or more logical blocks of a continuous logical address space interface (LBA interface) of a usual type of flash memory system with physical memory cell blocks. This assignment may be done by the host device which typically, but not necessarily, generates the data files. The number of logical blocks containing data of any one file is controlled in a manner that reduces the amount of fragmentation of file data within the physical memory blocks, thereby to maintain good memory performance. The host may configure the logical blocks of the address space in response to learning the physical characteristics of a memory to which it is connected.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.

Abstract: A program, method and system are disclosed for managing a snapshot backup restore through a hardware snapshot interface, i.e. a hardware-driven snapshot restore, based upon a software-driven snapshot backup, e.g. created with software such as volume shadow copy service (VSS). When conventional hardware-driven snapshot restores are performed using a snapshot backup that was created using the VSS-based software such as copy services, data access issues can arise, due to the operating system assigning of a new disk signature to the disk being restored. This problem can be overcome by temporarily storing the original disk signature and then overwriting the new, incorrect disk signature after initializing the restore. This can ensure that the operating system identifies the source LUNs (and accordingly, the drive letter and mount points of the disk) using the same disk signature as before the restore.

Abstract: A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache.

Abstract: An optical disk drive includes a non-volatile memory. The optical disk drive is booted based on driving information stored in the non-volatile memory. When a write command is received from a host, the optical disk drive stores data to be recorded in an optical medium in the non-volatile memory and then writes the data in the optical medium independent of the host.

Abstract: An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices.

Abstract: The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, an implementation is provided wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.

Abstract: Provided are an apparatus and method for processing data of flash memory. The apparatus includes a user requesting unit to request a data operation using a predetermined logical address, a transformation unit to transform the logical address into a physical address, and a control unit to record count data counting the number of predetermined bits of data, in an index region to indicate whether the data is valid when conducting the data operation.