Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.

Abstract: An apparatus, method, and computer program for facilitating disaster recovery of a first computer system, wherein first data residing on a first storage device associated with the first computer system is recoverable from second data residing on a second storage device associated with a second computer system and wherein the second storage device is operable to have an associated state of powered up or powered down. A receiver receives an update operation for updating the second storage device. A processor updates a non-volatile storage means with the update operation, prior to update of the second storage device, wherein the non-volatile storage means is associated with the second computer system.

Abstract: An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers without conflicts. The processors operate at different frequencies, while the servo-controller and the servo controller interface operate in same or different frequency domains. The pipeline control module resolves conflict between the first and second processor transaction. The speed matching module ensures communication without inserting wait states in a servo controller interface clock domain for write access to the servo controller and there is no read conflicts between the first and second processor. The controller also includes a hardware mechanism for indivisible register acess to the first or second processor. The hardware mechanisim includes a hard semaphore and/or soft semaphore.

Abstract: A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.

Abstract: A method, system, and computer program product for two-sided, dynamic cache injection control are provided. An I/O adapter generates an I/O transaction in response to receiving a request for the transaction. The transaction includes an ID field and a requested address. The adapter looks up the address in a cache translation table stored thereon, which includes mappings between addresses and corresponding address space identifiers (ASIDs). The adapter enters an ASID in the ID field when the requested address is present in the cache translation table. IDs corresponding to device identifiers, address ranges and pattern strings may also be entered. The adapter sends the transaction to one of an I/O hub and system chipset, which in turn, looks up the ASID in a table stored thereon and injects the requested address and corresponding data in a processor complex when the ASID is present in the table, indicating that the address space corresponding to the ASID is actively running on a processor in the complex.

Abstract: A method for writing data to a storage pool, including receiving a first write operation for a first block, determining a first replication type for the first block, determining a number of physical blocks (n1) required to write the first block to the storage pool using a size of the first block and the first replication type, if n1 is not a multiple of the maximum supported replication level of the storage pool: allocating a number of padded physical blocks (p1) to n1 until n1+p1 is a multiple of a maximum supported replication level of the storage pool, and writing the first block to the storage pool by filling in the n1 physical blocks.

Abstract: A data processing apparatus 2 includes a programmable general purpose processor 10 coupled to a hardware accelerator 12. A memory system 14, 6, 8 is shared by the processor 10 and the hardware accelerator 12. Memory system monitoring circuitry 16 is responsive to one or more predetermined operations performed by the processor 10 upon the memory system 14, 6, 8 to generate a trigger to the hardware accelerator 12 for it to halt its processing operations and clean any data values held as temporary variables within registers 20 of the hardware accelerator back to the memory system 14, 6, 8.

Abstract: Aspects of a method and system for an on-chip configurable data RAM for fast memory and pseudo associative caches are provided. Memory banks of configurable data RAM integrated within a chip may be configured to operate as fast on-chip memory or on-chip level 2 cache memory. A set associativity of the on-chip level 2 cache memory may be same after configuring the memory banks as prior to the configuring. The configuring may occur during initialization of the memory banks, and may adjusted the amount of the on-chip level 2 cache. The memory banks configured to operate as on-chip level 2 cache memory or as fast on-chip memory may be dynamically enabled by a memory address.

Abstract: One disclosed embodiment may comprise a system that includes a home node that provides a transaction reference to a requester in response to a request from the requester. The requester provides an acknowledgement message to the home node in response to the transaction reference, the transaction reference enabling the requester to determine an order of requests at the home node relative to the request from the requester.

Abstract: Methods and systems for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores are provided. Embodiments include receiving from a processor core a request to load a cache line in the shared cache; determining whether the shared cache is full; determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache.

Abstract: A data accessing system for interfacing between a smart card and a non-volatile memory is provided. The non-volatile memory has a smart card exclusive area accessible to a plurality of smart card applications. The smart card exclusive area includes a plurality of record unit sets respectively having a plurality of record units. The data accessing system has a buffer for temporarily storing data to be written into the smart card exclusive area and a data accessing protocol unit managing an access parameter table, a plurality of application information tables, and a plurality of record unit set link tables. The smart card applications access the smart card exclusive area in a unit of record unit set, and the size of a record unit set is a multiple of an access unit of the non-volatile memory.

Abstract: Where a first computing device is given responsibility for determining whether data that is time stamped by a second computing device is replicated or not, then the first device can compare a time stamp from the second device against a time signal from its own internal clock to determine a delta and use that delta to deduce the correct delta to apply to time stamps associated with later data from the second computing device.

Abstract: It is not uncommon for two or more wireless-enabled devices to spend most of their time in close proximity to one another. For example, a person may routinely carry a personal digital assistant (PDA) and a portable digital audio/video player, or a cellphone and a PDA, or a smartphone and a gaming device. When it is desirable to increase the memory storage capacity of a first such device, it may be possible to use memory on one or more of the other devices to temporarily store data from the first device.

Abstract: In a computer system an object of this invention is to reduce physical resource contentions during the parallel migration of volumes. The computer system of this invention has the host computers, the storage systems and the storage management server. When parallelly migrating two or more volumes of data in the storage systems to the same number of other volumes, the storage management server selects volumes having few physical conflicts of the controllers or storage devices in the storage systems and executes the parallel migration operation.

Abstract: An object of the present invention is to provide a means for detecting a logical command error, and a storage system and its control method that can properly perform error handling, and detection and blockage of a malfunctioning section. A storage control system includes controller units 130A and 130B for performing processing for data I/O to/from drives 150 and 160 in response to a data I/O request from a host device 100, switches 140A and 140B connecting the controller units 130A and 130B and the drives 150 and 160, and a port selector 300 inserted between the switches 140A and 140B and the drive 160. The port selector 300, when receiving a command generated based on processing performed by an MPU 131, accesses a target drive 160 if that data that forms a command is valid. Meanwhile, if the port selector 300 detects logical command inconsistency, the port selector 300 forwards that detection result to the MPU 131 via the switch 140A or 140B and requests retry processing from the MPU 131.

Abstract: A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find its startup logic and configuration data and begin executing. The shared memory system reduces the number of nonvolatile memory components used to initialize multiple processing components.

Abstract: In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.

Abstract: An architecture for managing a switched storage network consisting of one or more data storage volumes and one or more hosts. The data storage volumes are in a switched storage network. One or more processors provide the switching capability for the switched storage network. The one or more processors are capable of embodying logical constructions of a storage presentation layer and a volume presentation layer.

Abstract: In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.

Abstract: A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is supplying power to the RAID controller. A memory controller transfers the posted-write data received from the host computers to the volatile memory and transfers the posted-write data from the volatile memory for transfer to the redundant array of storage devices as managed by the CPU. The memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors.