Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.

Abstract: A storage interfacing method and apparatus for a mobile terminal are disclosed. The storage interfacing method utilizes a plurality of storage devices. The method includes identifying the storage devices, detecting an occurrence of an access request event to one of the identified storage devices, determining whether the access-requested storage device is an access-selected storage device, and performing, if the access-requested storage device is an access-selected storage device, a data transfer operation associated with the access request event on the access-selected storage device without access initialization and access-selection. The apparatus includes a first storage device supporting a MultiMediaCard (MMC) interface, a second storage device compatible with the MMC interface, and a control unit for controlling the first and second storage devices, according to the MMC interface, through control and data buses shared by the first and second storage devices.

Abstract: A method for operating a storage system, consisting of performing an allocation of respective partitions of a physical storage resource of the storage system to respective hosts of the storage system. The method also includes changing the allocation while permitting the respective hosts of the storage system to access the physical storage resource.

Abstract: In a virtualized system using memory page sharing, a method is provided for maintaining sharing when Guest code attempts to write to the shared memory. In one embodiment, virtualization logic uses a pattern matcher to recognize and intercept page zeroing code in the Guest OS. When the page zeroing code is about to run against a page that is already zeroed, i.e., contains all zeros, and is being shared, the memory writes in the page zeroing code have no effect. The virtualization logic skips over the writes, providing an appearance that the Guest OS page zeroing code has run to completion but without performing any of the writes that would have caused a loss of page sharing. The pattern matcher can be part of a binary translator that inspects code before it executes.

Abstract: A method for securing electronic device processes against attacks (e.g. side channel attacks) during the processing of sensitive and/or confidential data by a Central Processing Unit (CPU) to the volatile memory (e.g. RAM) of an electronic device such as, for example, a smart card, a PDA or a cellular phone is described herein. The method involves the storage of the confidential data to a dynamically and randomly assigned memory location, thereby rendering more difficult the analysis and subsequently the attacks (e.g. side channel attacks).

Abstract: A method that can simplify a recovery of a system. The method includes storing multiple types of information, and includes: a first stage of storing information representative of a content of a persistent memory entity at a certain point in time; and a second stage of storing information representative of a state of a virtual machine at the certain point in time; and recovering a system that associates between the first stage of storing information and the second stage of storing information.

Abstract: A method and system for sharing banks of memory in a multi-port memory device between components is provided. The multi-port memory device includes multiple ports to which components of a system are attached, and multiple banks of memory within the multi-port memory device that are shared by each of the ports. A bank availability pin is added to each port for each bank of memory. The bank availability pin is signaled when the bank is available to a particular port and unsignaled when the bank is unavailable. Thus, the multi-port memory device can be shared by several components simultaneously with only a small amount of additional hardware to support the sharing. Also provided are methods for refreshing the banks of memory.

Abstract: A refresh controller transmits two refresh request signals of a first request signal which indicates a time at which a refresh operation of a DRAM may be performed and a second request signal which indicates a time at which a refresh operation of the DRAM must be performed, to an arbitrator. On the other hand, also transfer request signals each of which requests a data transfer are transmitted from plural data transfer parts, respectively, to the arbitrator. If no transfer request signal is input when a first request signal is input to the arbitrator, a refresh operation of the DRAM is performed. As a result, a refresh operation is performed when the crowding level of a bus is relatively low. This improves an efficiency in a data transfer.

Abstract: A translator of an apparatus in an example selects one or more ranks of parallel memory devices from a plurality of available ranks of parallel memory devices in a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs) through employment of a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol).

Abstract: An apparatus and method for fairly accessing a shared cache with multiple resources, such as multiple cores, multiple threads, or both are herein described. A resource within a microprocessor sharing access to a cache is assigned a static portion of the cache and a dynamic portion. The resource is blocked from victimizing static portions assigned to other resources, yet, allowed to victimize the static portion assigned to the resource and the dynamically shared portion. If the resource does not access the cache enough times over a period of time, the static portion assigned to the resource is reassigned to the dynamically shared portion.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: Methods, apparatus, and products are disclosed for optimizing execution of Input/Output (‘I/O’) requests for a disk drive in a computing system that include: receiving I/O requests specifying disk blocks of the disk drive for access, each disk block specified by a disk drive head, a cylinder, and a sector of the disk drive; determining I/O sub-requests from the I/O requests, each I/O sub-request specifying a set of adjacent disk blocks along the same cylinder; determining execution sequences for performing the I/O sub-requests; calculating, for each execution sequence, a total estimated execution time for performing the I/O sub-requests according to that execution sequence; selecting one of the execution sequences for performing the I/O sub-requests in dependence upon the total estimated execution times for the execution sequences; and instructing a disk drive controller to perform the I/O requests by performing the I/O sub-requests according to the selected execution sequence.

Abstract: A method, system, and computer program manager for a computing system memory in the operation of a computing process. At least one memory segment provides memory resources for the computing process, which includes a plurality of memory objects, each of the memory objects includes an equal number of bytes and has a predetermined order that associates the address of the memory object in the memory segment to the addresses of the remainder of the plurality of memory objects. A pointer identifies a first memory object from the plurality of memory objects. The first memory object occupies a first ordered position according to the predetermined order. The process allocates the first memory objects from the memory segment during the operation of the computing process. The pointer increments to a second memory object having a second ordered position relative to the first memory object.

Abstract: The invention is an improvement to a storage virtualization system that enables the system to determine a class of service for potential storage devices and allows a user, administrator, or application to select a minimum class of service for any given type of data. The class of service is based upon factors that reflect a potential storage device's reliability, such as the device type and historical uptime data. In a P2P environment, the class of service also includes additional factors, such as the type of attached processing unit and the type of operating system running the attached processing unit.

Abstract: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a page table walker. The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.

Abstract: The present invention provides a system, method, and computer program product for reducing load imbalance in a storage system having a plurality of storage devices organized in one or more RAIDs for storing data by moving data from heavily-loaded storage devices to less-loaded storage devices during normal data access operations. As a result of moving data to less-loaded storage devices, the service latency of those storage devices decreases, thereby optimizing the system's performance.

Abstract: A system for protecting supervisor mode data from user code having a processor which implements a register window architecture supporting as separate window stacks for supervisor and user modes with a transition window in one of the window stacks set with at least one invalid window bit in an invalid window mask of the architecture additional to an invalid window bit set for a reserved window of the invalid window mask for transitioning from the supervisor mode to the user mode, supervisor mode-only memory storing the supervisor mode window stack, and user mode accessible memory storing the supervisor and user mode window stacks.

Abstract: An architecture for managing a plurality of storage area networks including a plurality of data storage volumes and one or more hosts, wherein the volumes are in a switched storage network in the storage area networks the architecture comprising one or more processors in communication with switching capability for the switched storage network, wherein the one or more processors include program logic for embodying logical constructions of a storage presentation layer including target virtualization and logical unit (LU) virtualization; and a volume presentation layer including volume virtualization for replication of data.

Abstract: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

Abstract: A rotating parity redundant array of independent disk (RAID) and a method for storing parity of the same are provided. The rotating parity RAID comprises a first˜a third disk. The first disk has A1˜Am blocks for storing A1˜Am data respectively. The second disk has B1˜Bm blocks for storing B1˜Bm data respectively. The third disk has C1˜Cm blocks for storing C1˜Cm data respectively. The Cn+k data is an nth parity data obtained from the An data and the Bn data. The Bn+k+1 data is an (n+1)th parity data obtained from the Cn+1 data and the An+1 data. The An+k+2 data is an (n+2)th parity data obtained from the Bn+2 data and the Cn+2 data.