Patents Examined by Shane M Thomas
  • Patent number: 7793047
    Abstract: An information processing apparatus includes: a main memory that stores data; a plurality of processors each provided with a primary cache memory; a secondary cache memory that is provided between the main memory and the processors, the secondary cache memory having larger capacity than the primary cache memory; and a cache controller that performs cache search on the secondary cache memory based on a second index uniquely generated by joining: 1) a bit string having a predetermined bit length; and 2) a first index that is included in a data access command transmitted from any one of the processors, the first index being used for performing cache search on the primary cache memory.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: September 7, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigehiro Asano
  • Patent number: 7788449
    Abstract: A computer-implemented method is disclosed. The method includes collecting cache-efficiency-indicator values of an at least one cache fragment during operation of a database system over a period of time. Providing approximation-function-parameter values for the collected, cache-efficiency-indicator values, an approximation function representing a relation between a cache-efficiency-indicator and the size of a respective cache fragment. The method continues by providing a set of workload windows based on the approximation-function-parameter values. Next, providing a workload-window information for the set of workload windows, the workload-window information including at least one approximation-function-parameter value representing each determined workload window. The method further includes storing the workload-window information for a comparison based on current, cache-efficiency-indicator values and the workload-window information.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Holger Karn, Sven Miller
  • Patent number: 7783851
    Abstract: Methods of operating a non-volatile memory device that includes a first data block that stores first data and a first log block that stores an updated version of at least some of the first data is provided in which valid portions of the first data in the first data block are copied to a free block that has no data to generate a second data block. The updated version of at least some of the first data from the first log block is copied to the second data block. The first log block is designated as a reusable log block without erasing the data therefrom in response to at least one predetermined condition being satisfied.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Been Im, Hye-Young Kim
  • Patent number: 7783855
    Abstract: Various embodiments of a computer-implemented method, system and computer program product are provided. A first plurality of key entries of a first index page are compressed in accordance with an order specified by a first keymap of the first index page. The first keymap also indicates respective positions of the key entries of the first plurality of key entries. A second keymap is generated indicating the order and also indicating respective post-compression positions of the key entries of the first plurality of key entries. The compressed first plurality of key entries is stored on a second index page with the second keymap.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventors: Sauraj Goswami, You-Chin Fuh, Michael R. Shadduck, James Zu-Chia Teng
  • Patent number: 7783853
    Abstract: A method of operating real-time middleware associated with at least one node of a data distribution system is provided. At least one pool of a plurality of fixed block size units of memory of the node is allocated (e.g., via an operating system call). Based on loan requests for dynamic memory elements on behalf of a user application executing on the node, an indication of at least one of the allocated fixed block size units to be lent is provided. A list of which allocated fixed block size units are being lent from the pool is maintained, including maintaining the list based on return requests, on behalf of the user application executing on the node, of fixed block size units of the pool. Substantially all of the dynamic memory elements of the real-time middleware associated with the node are provided from the at least one pool of allocated fixed block size units based on the loan requests on behalf of the user application.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: August 24, 2010
    Assignee: Real-Time Innovations, Inc.
    Inventors: Stephen Jisoo Rhee, Yi Dai, Gerardo Pardo-Castellote, Rajive Joshi
  • Patent number: 7774541
    Abstract: A storage apparatus using a non-volatile memory, which retains data even after power interruption, as its cache and a method of managing the same are provided. The storage apparatus includes a main storage medium, a non-volatile memory used as a cache of the main storage medium, a region of the non-volatile memory being divided into a fixed region and a non-fixed region according to whether or not data is fixed, and a block management unit managing physical blocks by means of virtual addresses, the physical blocks being allocated to the non-volatile memory.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: August 10, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kun Shin, Shea-yun Lee, Jang-hwan Kim, Dong-hyun Song
  • Patent number: 7774570
    Abstract: The storage virtualization switch is capable of correctly designating a virtual target when a host computer accesses the virtual target. A dummy virtual target, which corresponds to a virtual target, is put into an effective state after the virtual target is put into the ineffective state when the virtual target is put into the ineffective state, and the virtual target is put into an effective state after the dummy virtual target, which corresponds to the virtual target, is put into the ineffective state when the virtual target is put into the effective state.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: August 10, 2010
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Kinoshita, Toshitaka Yanagisawa, Takaaki Yamato, Toshiaki Takeuchi, Jun Takeuchi, Atsushi Shinohara, Yusuke Kurasawa
  • Patent number: 7774542
    Abstract: Apparatus and methods for efficiently operating on RAID systems. A fast access buffer comprising an off-disk fast access memory module supports RAID operations such as recovery or reconfiguration operations, thereby minimizing or reducing the need for on-disk destructive zones and/or reducing disk drive I/O activities. In some cases the fast access memory module to serves as a read/write cache, reducing the need for frequent disk accesses of a small number of data blocks. Fast off-disk memory such as RAM enables rapid operation on in-buffer data blocks. Access to the material stored in the RAID devices may be enabled, partially enabled or disabled during RAID operations involving the fast access memory module and some data access operations may be synchronized with RAID operations. In some cases, data may be served from the fast access memory module, thereby providing rapid access to material stored in a RAID device during RAID operations.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: August 10, 2010
    Inventors: Ji Zhang, Hain-Ching Liu, Jian Gang Ding
  • Patent number: 7765361
    Abstract: To ensure that logs representative of data changes are durably written, localized storage media cache is flushed to force a write to stable storage. Log sequence number tracking is leveraged to determine if log data in a localized storage media cache is likely to have not been written to durable storage. When this condition is likely, a FLUSH_CACHE command is issued to a storage media controller to force a durable write. This allows recovery of data changes to a transactional system even when its associated storage media does not provide write-ordering guarantees. Moreover, flushing of the storage media cache can be accomplished at a frequency that provides an upper bound on a maximum time between a transaction commit and data being made durable.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: July 27, 2010
    Assignee: Microsoft Corporation
    Inventors: Robin Dhananjay Dhamankar, Vishal Kathuria, Sethu Kalavakur, Gayathri Venkataraman, Avraham Levy, Hanumantha Rao Kodavalla, Chunjia Li, Eric Ray Christensen
  • Patent number: 7761669
    Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Brian David Allison, Wayne Barrett, Joseph Allen Kirscht, Elizabeth A. McGlone, Brian T. Vanderpool
  • Patent number: 7752387
    Abstract: A storage system includes a RAID adapter, disk array switches, sub-processors, and hard disk drives. A disk-related operation is initiated in the RAID adapter which dispatches a command to a disk array processor (or sub-processor) in an enclosure for the processor to perform the operation on one or more drives. The adapter may dispatch the command to a processor in a single enclosure through a disk array switch or to processors in multiple enclosures through switches in upstream enclosures. The adapter is then free to perform other functions. The processor commences the specified operation on one or more selected drives. Upon completion of the operation, the results are transmitted by the processor and received by the adapter. Offloading the task to the distributed sub-processors reduces the burden on the RAID adapter, reduces system bandwidth usage, and enables access to other drives to be maintained.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: John C. Elliott, Robert A. Kubo, Gregg S. Lucas, Kenneth J. Hallam, Pauline Hallam, legal representative
  • Patent number: 7752386
    Abstract: Responding to IO requests made by an application to an operating system within a computing device implements IO performance acceleration that interfaces with the logical and physical disk management components of the operating system and within that pathway provides a system memory based disk block cache. The logical disk management component of the operating system identifies logical disk addresses for IO requests sent from the application to the operating system. These addresses are translated to physical disk addresses that correspond to disk blocks available on a physical storage resource. The disk block cache stores cached disk blocks that correspond to the disk blocks available on the physical storage resource, such that IO requests may be fulfilled from the disk block cache.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: July 6, 2010
    Assignee: DataCore Software Corporation
    Inventors: Ziya Aral, Roni J. Putra
  • Patent number: 7743202
    Abstract: The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: June 22, 2010
    Assignee: Mediatek Inc.
    Inventors: Chung-Hung Tsai, Ming-Shiang Lai
  • Patent number: 7739444
    Abstract: Data files are assigned addresses within one or more logical blocks of a continuous logical address space interface (LBA interface) of a usual type of flash memory system with physical memory cell blocks. This assignment may be done by the host device which typically, but not necessarily, generates the data files. The number of logical blocks containing data of any one file is controlled in a manner that reduces the amount of fragmentation of file data within the physical memory blocks, thereby to maintain good memory performance. The host may configure the logical blocks of the address space in response to learning the physical characteristics of a memory to which it is connected.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: June 15, 2010
    Assignee: SanDisk Corporation
    Inventors: Alan W. Sinclair, Barry Wright
  • Patent number: 7734879
    Abstract: A technique for efficiently boosting the priority of a preemptable data reader in order to eliminate impediments to grace period processing that defers the destruction of one or more shared data elements that may be referenced by the reader until the reader is no longer capable of referencing the data elements. Upon the reader being subject to preemption or blocking, it is determined whether the reader is in a read-side critical section referencing any of the shared data elements. If it is, the reader's priority is boosted in order to expedite completion of the critical section. The reader's priority is subsequently decreased after the critical section has completed. In this way, delays in grace period processing due to reader preemption within the critical section, which can result in an out-of-memory condition, can be minimized efficiently with minimal processing overhead.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Paul E. McKenney, Suparna Bhattacharya
  • Patent number: 7734868
    Abstract: A RAID class driver model enables users to easily combine two or more disks into a bootable RAID system without specialized disk controllers and allows the creation of RAID systems using disks of different types, controllers, and interfaces. A RAID class driver is initialized in response to the identification of a RAID controller. Disk controllers return RAID-specific device identifications, rather than a standard disk device identifications, for each disk to be included in the RAID system. The RAID class driver binds a RAID-specific functional interface to each disk having a RAID-specific device identification and combines the disks into a disk object representing the entire RAID system. The disk object provides the operating system with a standard disk device identification. The operating system loads a standard disk driver to interface with the disk object, thereby enabling transparent access to the RAID system.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: June 8, 2010
    Assignee: NVIDIA Corporation
    Inventor: Qiming Zhu
  • Patent number: 7725674
    Abstract: Systems, apparatuses and methods for erasing hard drives. A system, which can be configured as a stand alone and portable apparatus, includes a control device configured to support an erase module. The erase module is configured to erase a hard drive such that data erased from the hard drive is forensically unrecoverable. The system further includes a user interface and at least one drive bay configured to provide communication between a hard drive and the control device.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: May 25, 2010
    Assignee: Ensconce Data Technology, Inc.
    Inventor: Jack D. Thorsen
  • Patent number: 7721056
    Abstract: The present invention proposes a storage system having a plurality of disk array apparatuses managed separately by different managers, that can considerably improve the reliability of data backup. The invention provides a storage system, in which a first disk array apparatus includes a storing unit for storing volume information, which is information about the configuration of the volume; an extracting unit for, when receiving an external backup instruction, extracting, according to the backup instruction, volume information, as backup volume information from the volume information stored in the storage unit, about a backup target volume; and a presenting unit for presenting the backup volume information extracted by the extracting unit to an external device, and the second disk array apparatus includes an allocating unit for allocating a corresponding second volume to the backup target volume by referring to the backup volume information presented by the presenting unit.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: May 18, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Hiroshi Wake
  • Patent number: 7721047
    Abstract: In view of the foregoing, the shortcomings of the prior art cache optimization techniques, the present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, an application requests a kernel cache map from a kernel service and the application receives the kernel. The application designs an optimum cache footprint for a data set from said application. The objects, advantages and features of the present invention will become apparent from the following detailed description. In one embodiment of the present invention, the application transmits a memory reallocation order to a memory manager. In one embodiment of the present invention, the step of the application transmitting a memory reallocation order to the memory manager further comprises the application transmitting a memory reallocation order containing the optimum cache footprint to the memory manager.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: May 18, 2010
    Assignee: International Business Machines Corporation
    Inventors: Andrew Dunshea, Diane Garza Flemming
  • Patent number: 7716422
    Abstract: Provided are a storage apparatus using a non-volatile memory as a cache and a method of operating the same, in which the non-volatile memory is used as the cache so as to preserve data even when electricity is interrupted. The storage apparatus using a non-volatile memory as a cache includes a main storage medium, the non-volatile memory being used as the cache of the main storage medium and having a stationary region and a non-stationary region divided according to whether data are fixed, and a block management unit managing blocks allocated in the non-volatile memory.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: May 11, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kun Shin, Sang-lyul Min, Shea-yun Lee, Jang-hwan Kim, Dong-hyun Song, Jeong-eun Kim