Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.

Abstract: A semiconductor device according to an embodiment includes a first GaN based semiconductor layer of a first conductive type, a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer, a epitaxially grown fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, a gate insulating film provided on the second, third, and fourth GaN based semiconductor layer, a gate electrode provided on the gate insulating film, a first electrode provided on the fourth GaN based semiconductor layer, a second electrode provided at the side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer, and a third electrode provided on the second GaN based semiconductor layer.

Abstract: A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features, performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features, after the etching process, forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features, forming a semiconductor layer over the anti-punch-through features, and forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features.

Abstract: Disclosed is an array substrate, a method for manufacturing the same, and a display device. The array substrate includes: a base substrate and a plurality of data lines disposed on the base substrate. The base substrate comprises a plurality of attaching areas in which the end of each data line attaches to the base substrate, and non-attaching areas between each two adjacent attaching areas, and a height layer is disposed between a passivation layer and the base substrate in the non-attaching area. By interposing a height layer between the passivation layer and the base substrate in the non-attaching area, the height difference between the passivation layer in the attaching area and the non-attaching area is decreased or disappeared, then the problem of fall-off of the passivation layer is solved, and the reliability of the product is increased.

Abstract: A method for forecasting reduction in sunlight intensity due to cloud cover at a photovoltaic power plant is described. The method comprises determining characteristics of one or more clouds from sensors surrounding the photovoltaic power plant. The cloud characteristics are used to create a 3D map of the clouds. The 3D map in combination with information on the angle of the sun is used to create a 3D projection on the surface of the earth, resulting in a 2D surface irradiance map. The 2D surface irradiance map may be taken in successive projections or used in combination with wind speed data to forecast fluctuation in irradiance at the photovoltaic power plant. The forecasted reductions in power may be used to enact measures at the plant such as reducing the power output of inverters to prevent sudden fluctuations in the power output of the photovoltaic plant feeding the utility.

Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed on the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a dielectric layer having a first portion and a second portion, wherein the first portion of the dielectric layer is formed on a portion of the gate structure, and the second portion of the dielectric layer is formed on the substrate and extending to a portion of the drain region, wherein the dielectric layer includes at least one recess on the second portion. An associated fabricating method is also disclosed.

Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.

Abstract: A light emitting device has a lens, extended to outside of the mounting substrate on which a semiconductor a light emitting element is mounted, and leakage of light is reduced. A light emitting element, a substrate having the light emitting element mounted on its upper surface, and a lens, having a curved upper surface encloses the light emitting element and the upper surface of the substrate is included. From the bottom surface of the lens, a lower surface of the substrate is exposed. In a top view from a perpendicular direction to the upper surface of the substrate, the bottom surface of the lens includes an outer extending portion where the bottom surface is extended to outside of the substrate, and a inclined portion, which inclines with respect to a direction approximately in parallel to the upper surface of the substrate, at an end portion of the outer extending portion.

Abstract: A flat display panel and manufacturing method are disclosed. The flat display panel includes a first substrate, a second substrate disposed oppositely to the first substrate. The second substrate is provided with a material layer having multiple concave slots. Multiple spacers are disposed on the first substrate and facing toward the second substrate. Wherein, multiple spacers include multiple main spacers and auxiliary spacers. The multiple auxiliary spacers respectively face toward regions which the multiple concave slots are located on, and the multiple main spacers respectively face toward regions which the multiple concave slots are not located on. A height of each main spacer and a height of each auxiliary spacer are the same such that when the flat display panel is not pressed, supporting the flat display panel through the main spacers, and when the flat display panel is pressed, further supporting the flat display panel through the auxiliary spacers.

Abstract: Provided is a method for manufacturing a semiconductor device with favorable electrical characteristics. The following steps are performed in the following order: forming an oxide semiconductor film over a substrate having a substantially planar surface; selectively etching the oxide semiconductor film to form an oxide semiconductor layer; implanting an oxygen ion on a top surface of the oxide semiconductor layer and a side surface of the oxide semiconductor layer in a cross-section perpendicular to the substantially planar surface in a channel width direction of the oxide semiconductor layer from an angle 0°<?<90°; forming an insulating layer over the oxide semiconductor layer, and performing heat treatment on the oxide semiconductor layer to diffuse oxygen into the oxide semiconductor layer.

Abstract: Provided are a photoelectric conversion device, a method of manufacturing the photoelectric conversion device, and an X-ray image detector. A photoelectric conversion device at least includes a photodiode device. The photodiode device includes a lower electrode and an upper electrode, and a photoelectric conversion layer put between the lower and upper electrodes, where the photoelectric conversion layer includes a patterned edge surface, is smaller in size than the lower electrode and is placed on a surface of the lower electrode. The photodiode device further includes a protecting film covering at least the patterned edge surface of the photoelectric conversion layer. The protecting film except for an area where a contact hole is formed and the lower electrode are formed with a same-shaped pattern.

Abstract: A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.

Abstract: The present invention provides a complementary thin film transistor and a manufacturing method thereof, an array substrate and a display apparatus, relates to the field of manufacturing technology of thin film transistor, and can solve the problem that active layer materials of first and second thin film transistors in a complementary thin film transistor of the prior art have influence with each other. The manufacturing method of the present invention comprises steps of: forming a pattern comprising an active layer of a first thin film transistor and a protective layer on a base by a patterning process, and the protective layer is at least located above the active layer of the thin film transistor; and forming a pattern of an active layer of a second thin film transistor on the base subjected to above step by a patterning process. The present invention may be applied to various circuits and systems.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

Abstract: Disclosed herein is a light-emitting device. The light-emitting device includes a substrate; a first light-emitting unit and a second light-emitting unit, separately formed on the substrate; a trench between the first and the second light-emitting units, including a bottom portion exposing the substrate; an insulating layer, comprising a first part formed on the first light-emitting unit or the second light-emitting unit, and a second part conformably formed on the trench covering the bottom portion and sidewalls of the first light-emitting unit and the second light-emitting unit; and an electrical connection, electrically connecting the first light-emitting unit and the second light-emitting unit, comprising a bridging portion formed on the second part of the insulating layer, and only covering a portion of the trench; and a joining portion, extending from the bridging portion and formed on the first part of the insulating layer; wherein the bridging portion is wider than the joining portion in a top view.

Abstract: The present invention provides method for manufacturing an AMOLED backplane and a structure thereof. The method uses a drain terminal of a drive TFT to serve as an anode of AMOLED the anode, so that compared to the prior art, the steps of forming a planarization layer and an anode layer are eliminated and also, the same half-tone masking operation is used to form a pixel definition layer and photo spacers, whereby the method for manufacturing the AMOLED backplane according to the present invention requires only six masking operations and saves three masking operations compared to the prior art, thereby effectively simplifying the manufacturing process, improving manufacturing efficiency, and saving cost. The present invention provides a structure of an AMOLED backplane, which has a simple structure, is easy to manufacture, and has a low cost.

Abstract: Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.

Abstract: A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.