Abstract: The present disclosure relates to a vertical bipolar junction transistor. A vertical bipolar junction transistor includes a high concentration doping region emitter terminal disposed on a semiconductor substrate; a high concentration doping region collector terminal disposed on a semiconductor substrate; a high concentration doping region base terminal disposed between the emitter terminal and the collector terminal; a drift region having a first doping concentration surrounding the emitter terminal and being deeper than either the base terminal or the collector terminal; a base layer disposed below the drift region; a collector layer in contact with the base layer, the collector layer having a second doping concentration higher than the first doping concentration. The manufacturing cost of the vertical bipolar junction transistor can be lowered and a current gain can be elevated using a low-cost BCD process.

Abstract: A semiconductor light emitting device that is excellent in radiating heat and that can be molded into a sealing shape having intended optical characteristics by die molding is provided. The semiconductor light emitting device includes: a lead frame including a plate-like semiconductor light emitting element mounting portion having an LED chip mounted on a main surface, and a plate-like metal wire connecting portion extending over a same plane as the semiconductor light emitting element mounting portion; a metal wire electrically connecting the LED chip and the metal wire connecting portion; a thermosetting resin molded by die molding or dam-sheet molding so as to completely cover the LED chip and the metal wire; and a resin portion provided to surround the lead frame and having the thickness not greater than the thickness of the lead frame.

Abstract: A method of manufacturing a thin film transistor substrate includes forming an amorphous silicon layer on a substrate, the substrate having a rectangular shape, and irradiating the amorphous silicon layer with a laser beam at a random pitch, such that the amorphous silicon layer is crystallizes into a polycrystalline silicon layer, wherein the laser beam has a major axis and a minor axis, the major axis being non-parallel with respect to sides of the substrate.

Abstract: Provided are a method of manufacturing semiconductor device, a substrate processing apparatus and a recording medium which are capable of efficiently removing a deposited film in a shower head and suppressing generation of particles. The method of manufacturing a semiconductor device includes (a) forming a film on a substrate by supplying a film forming gas and an inert gas to the substrate in a processing chamber via a shower head, and (b) removing a deposited film deposited in the shower head in (a) by supplying to the shower head an inert gas, which has a temperature lower than that of the inert gas supplied in (a), into the shower head without the substrate loaded in the processing chamber.

Abstract: A light-emitting diode including a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer and having a conductivity type different than that of the first semiconductor layer, and a reflective pattern disposed on the second semiconductor layer and configured to reflect light emitted from the active layer, the reflective pattern having heterogeneous metal layers and configured to absorb stress caused by differences in coefficient of thermal expansion between the heterogeneous metal layers.

Abstract: Embodiments of methods for forming features in a silicon containing layer of a substrate disposed on a substrate support are provided herein. In some embodiments, a method for forming features in a silicon containing layer of a substrate disposed on a substrate support in a processing volume of a process chamber includes: exposing the substrate to a first plasma formed from a first process gas while providing a bias power to the substrate support, wherein the first process gas comprises one or more of a chlorine-containing gas or a bromine containing gas; and exposing the substrate to a second plasma formed from a second process gas while no bias power is provided to the substrate support, wherein the second process gas comprises one or more of an oxygen-containing gas or nitrogen gas, and wherein a source power provided to form the first plasma and the second plasma is continuously provided.

Abstract: The present invention provides a TFT and a manufacturing method thereof, an array substrate and a display device. The TFT comprises a gate, an active layer located on the gate, an ohmic contact layer located on the active layer, and a first electrode and a second electrode located on the ohmic contact layer, wherein the first electrode and the second electrode are partially overlapped with the active layer, the ohmic contact layer is located within a region where the first electrode and the second electrode are overlapped with the active layer; the active layer is partially overlapped with the gate, the active layer comprises at least one opening region partially overlapped with the gate; and the first electrode and/or the second electrode extends beyond the active layer through the at least one opening region.

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

Abstract: A light emitting device is disclosed. The light emitting device includes: a light emitting diode emitting light having a peak wavelength in the range of 415 nm to 435 nm; and a wavelength conversion unit disposed on the light emitting diode, wherein the wavelength conversion unit includes cyan phosphors emitting light having a peak wavelength in a cyan light wavelength band and red phosphors emitting light having a peak wavelength in a red light wavelength band, and a ratio of an output of light having a wavelength in the range of 435 nm to 465 nm to a total output of light emitted from the light emitting device is approximately equal to or less than 3%.

Abstract: A volumetric integrated circuit manufacturing method is provided. The method includes assembling a slab element of elongate chips, exposing a wiring layer between adjacent elongate chips of the slab element, metallizing a surface of the slab element at and around the exposed wiring layer to form a metallized surface electrically coupled to the wiring layer and passivating the metallized surface to hermetically seal the metallized surface.

Abstract: A method of manufacturing a semiconductor device includes forming a device structure in a surface of a semiconductor substrate, forming, in a face of the semiconductor substrate, a transition metal layer that contacts the semiconductor substrate, and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves to cause the transition metal layer to generate heat. During exposure of the semiconductor substrate to the hydrogen plasma atmosphere, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of the heat from the transition metal layer, and an ohmic contact is formed at an interface of the transition metal layer and the semiconductor substrate by reaction of the transition metal layer and the semiconductor substrate. When the semiconductor substrate is silicon carbide, the ohmic contact is composed of a silicide, such as a transition metal silicide.

Abstract: A semiconductor light emitting device includes a light emitting structure and first and second electrodes. The light emitting structure includes first and second conductivity type semiconductor layers and an active layer interposed therebetween. The first and second electrodes are electrically connected to the first and second conductivity type semiconductor layers. The second electrode includes a current blocking layer, a reflective part disposed on the current blocking layer, a transparent electrode layer disposed on the second conductivity type semiconductor layer, a pad electrode part disposed within a region of the current blocking layer, and at least one finger electrode part disposed at least in part on the transparent electrode layer. The transparent electrode layer can be spaced apart from the reflective part, and have an opening surrounding the reflective part. In some examples, the transparent electrode layer can further be spaced apart from the current blocking layer.

Abstract: A heat dissipation structure of an SMD LED includes a substrate, an SMD LED and at least one engaging member. A plurality of conductive copper foils is covered on an upper end face of the substrate. Two electrodes are provided on a lower surface of the SMD LED and are respectively connected to two copper foils on the upper end face. An engaging hole extends through one of the copper foils adjacent the SMD LED and through the substrate. The engaging member is made of high thermal conductive metal and is engaged in the engaging hole to combine the copper foil and the substrate. Accordingly, heat generated by the SMD LED can be directly transferred to an exposed lower end face of the substrate through the engaging member for more heat dissipation and less luminance decrease of the SMD LED.

Abstract: A semiconductor light emitting device includes a substrate, a reflective layer and a light emitting structure. The reflective layer includes at least two porous layers alternately disposed on the substrate and having different porosities. The light emitting structure is disposed on the reflective layer and includes a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer.

Abstract: A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width over a major surface of a substrate, forming a stack of alternating material layers over the etch stop layer, etching the stack to the etch stop layer to form a memory opening having a second width at a bottom of the memory opening that is smaller than the width of the etch stop layer, removing the etch stop layer to provide a void area having a larger width than the second width of the memory opening, forming a memory film over a sidewall of the memory opening and in the void area, and forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening.

Abstract: The present invention provides a method for manufacturing an array substrate, an array substrate, and a display device. The method for manufacturing an array substrate, including a step of forming a thin film transistor and a storage capacitor on a substrate, the thin film transistor including a gate, a source, and a drain, and the storage capacitor including a first pole plate and a second pole plate, wherein, arranging the source, the drain, and the first pole plate in a single layer through implanting dopant ions into an amorphous silicon layer formed on the substrate by one ion-implantation process, and through crystallizing an amorphous silicon material forming the amorphous silicon layer and activating the dopant ions by a laser irradiation process. Accordingly, process steps are simplified and a process cost is reduced greatly, and the performances of the array substrate and the display device are increased.

Abstract: A semiconductor device includes a MIM capacitor on a substrate. The MIM capacitor includes a dielectric region and first and second electrodes on opposite sides of the dielectric region. At least one of the first and second electrodes, e.g., an upper electrode, includes an oxygen diffusion blocking material, e.g., oxygen atoms, at a concentration that decreases in a direction away from the dielectric region. The at least one of the first and second electrodes may include a first layer having a first concentration of the oxygen diffusion blocking material and a second layer on the first layer and having a second concentration of the oxygen diffusion blocking material less than the first concentration. The at least one of the first and second electrodes may further include a third layer on the second layer and having a concentration of the oxygen diffusion blocking material less than the second concentration.

Abstract: A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.

Abstract: The present invention provides a semiconductor device that can achieve both low on-resistance and high withstand voltage, while reducing the device size, improving the manufacturing yield, and reducing the cost. The semiconductor device 1 includes a substrate 5, an epitaxial layer 6 formed on the substrate 5 and formed with a gate trench 11, a gate insulating film 17 formed on the side surface 14 and the bottom surface 15 of the gate trench 11, a gate electrode 20 embedded in the gate trench 11 and opposed to the epitaxial layer 6 with the gate insulating film 17 therebetween, and a source layer 25, a channel layer 26, and a drift layer 27 formed in this order from a first surface to a second surface of the epitaxial layer 6, in which the on-resistance Ron represented by a variable “y” and the withstand voltage Vb represented by a variable “x” functionally satisfy the following relational expression (1): y?9×10?7x2?0.0004x+0.7001??(1).

Abstract: A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.