Abstract: The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.

Abstract: An organic light emitting diode display is provided including: a substrate including a display area and a non-display area positioned at a circumference of the display area; a thin film transistor formed on the substrate; a first electrode formed on the thin film transistor and electrically connected to the thin film transistor; a pixel definition layer formed on the first electrode and defining a pixel area; and an emission layer formed on the first electrode and contacting the first electrode in the pixel area, wherein the display area is divided into a first region, and a second region including a remainder of the display area except for the first region, and a cross-sectional area ratio of the pixel definition layer that a cross-section of the pixel definition layer occupies for a unit pixel is different in the first region and the second region.

Abstract: A semiconductor device may include the following elements: a first substrate; a second substrate; a dielectric layer, which may be positioned between the first substrate and the second substrate and may have a hole; a first conductive member, which may be positioned in the dielectric layer; a second conductive member, which may be positioned in the dielectric layer, may be spaced from the first conductive member, and may be positioned closer to the second substrate than the first conductive member; and a third conductive member, which may contact both the first conductive member and the second conductive member through the hole.

Abstract: A first semiconductor chip has a first electrode pad, and a second semiconductor chip has a first through via and a second electrode pad joined to the via and aligned with the first electrode pad. A third semiconductor chip has a second through via, a third electrode pad joined to the via, wiring joined to the via, and a fourth electrode pad joined to the wiring and aligned with the second and third electrode pads. The semiconductor chips are stacked and electrically connected by joining the first to third electrode pads to one another, and gaps of the stacked body are filled with resin. The stacked body is secured to an adhesive material formed on a substrate and a solder bump formed on the substrate is joined to the fourth electrode. A molding resin encapsulates the stacked body and an adjacent surface of the substrate.

Abstract: A display substrate includes a base substrate, a common line on the base substrate, a first insulation layer covering the common line and having a first insulating material, a conductive pattern on the first insulation layer and including a source electrode and a drain electrode, a second insulation layer covering the drain electrode and the common line, and including a lower second insulation layer having a second insulating material and an upper second insulation layer having the first insulating material, a first electrode electrically connected to the drain electrode through a first contact hole in the second insulation layer, and a second electrode electrically connected to the common line through a second contact hole in the first and second insulation layers. The upper and lower second insulation layers on the drain electrode have a first hole and a second hole respectively that form the first contact hole.

Abstract: Provided are an organic light-emitting display apparatus having superior light efficiency and ease of manufacture, as well as a method of manufacturing the same. The organic light-emitting display apparatus includes: a substrate; a pixel electrode disposed on a pixel region of the substrate; a first insulating layer that is interposed between the substrate and the pixel electrode and that has a first discontinuous region extending along at least a portion of an edge of the pixel electrode; an intermediate layer that is disposed on the pixel electrode and that includes an emission layer; and an opposite electrode that covers the intermediate layer and at least a portion of the first discontinuous region, so that a shortest distance to the substrate in at least a portion of the first discontinuous region is shorter than a shortest distance between the pixel electrode and the substrate.

Abstract: The present invention provides a polysilicon thin-film transistor array substrate and a method for preparing the same, and a display device, wherein the method comprises a step of forming a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode of the polysilicon thin-film transistor, and a first electrode and a second electrode of a storage capacitor, and a gate line and a data line, wherein, the semiconductor layer and the first electrode of the storage capacitor are formed via a one-time patterning process, and the gate electrode, the gate line and the second electrode of the storage capacitor are formed via a one-time patterning process. By the solution of the invention, the number of mask plates used can be lowered, so that the process can be simplified, and the production cost can be lowered.

Abstract: Provided are methods of fabricating memory cells such as resistive random access memory (ReRAM) cells. A method involves forming a first layer including two high-k dielectric materials such that one material has a higher dielectric constant than the other material. In some embodiments, hafnium oxide and titanium oxide form the first layer. The higher-k material may be present at a lower concentration. In some embodiments, a concentration ratio of these two high-k materials is between about 3 and 7. The first layer may be formed using atomic layer deposition. The first layer is then annealed in an oxygen-containing environment. The method may proceed with forming a second layer including a low-k dielectric material, such as silicon oxide, and forming an electrode. After forming the electrode, the memory cell is annealed in a nitrogen containing environment. The nitrogen anneal may be performed at a higher temperature than the oxygen anneal.

Abstract: A selective wet etching process is used, prior to air gap opening formation, to remove a sacrificial nitride layer from over a first region of an interconnect dielectric material containing a plurality of first conductive metal structures utilizing a titanium nitride hard mask portion located over a second region of the interconnect dielectric material as an etch mask. The titanium nitride hard mask portion located over the second region of the interconnect dielectric material is thereafter removed, again prior to air gap opening formation, utilizing another wet etch process. The wet etching processes are used instead of reactive ion etching.

Abstract: A thin-film transistor includes a substrate, a first gate electrode formed on the substrate, a first active layer that is formed on the substrate and includes a first oxide semiconductor layer and a first barrier layer, a second active layer that is formed on the first active layer and includes a second oxide semiconductor layer and an intermediate barrier layer, a gate insulating layer that is formed on the second active layer, a second gate electrode that is formed on the gate insulating layer and is electrically connected to the first gate electrode, an interlayer insulating film formed on the second gate electrode, the first active layer and the second active layer, and a source electrode and a drain electrode electrically connected to the first active layer and the second active layer.

Abstract: The present disclosure provides a method of fabricating a semiconductor device with metal interconnections and a design of a tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device, the method includes providing a semiconductor substrate, depositing a dielectric layer over the semiconductor substrate, forming at least one trench in the dielectric layer, and forming a metallization layer in the trench and over the dielectric layer. The method further includes performing a chemical mechanical polishing process to planarize the metallization layer and the dielectric layer, performing a surface treatment on the planarized dielectric layer to form a protection layer, cleaning the planarized metallization layer and the treated dielectric layer to remove residue from the chemical mechanical polishing process, and drying the cleaned metallization layer and dielectric layer in an inert gas environment.

Abstract: A photoelectronic element includes an electrically insulative substrate, an electrically conductive substrate, an intermediate layer and a semiconductor stacked layer. The electrically insulative substrate has a top surface. The electrically conductive substrate has a lower portion, and an upper portion surrounded by the electrically insulative substrate and coplanar with the top surface. The intermediate layer has a first portion formed directly under the electrically insulative substrate and above the electrically conductive substrate, a second portion and a bent portion formed between the first portion and the second portion. The semiconductor stacked layer has an light-emitting active layer with a high band gap, disposed on the electrically insulative substrate and the upper portion.

Abstract: A low Rdson LDMOS transistor having a shallow field oxide region that separates a gate electrode of the transistor from a drain diffusion region of the transistor. The shallow field oxide region is formed separate from the field isolation regions (e.g., STI regions) used to isolate circuit elements on the substrate. Fabrication of the shallow field oxide region is controlled such that this region extends below the upper surface of the semiconductor substrate to a depth that is much shallower than the depth of field isolation regions. For example, the shallow field oxide region may extend below the upper surface of the substrate by only Angstroms or less. As a result, the current path through the resulting LDMOS transistor is substantially unimpeded by the shallow field oxide region, resulting in a low on-resistance.

Abstract: The present invention provides a regenerative nanosensor device for the detection of one or more analytes of interest. In certain embodiments, the device comprises a nanostructure having a reversible functionalized coating comprising a supramolecular assembly. Controllable and selective disruption of the assembly promotes desorption of at least part of the reversible functionalized coating thereby allowing for reuse of the regenerative device.

Abstract: The present invention provides a solid-state imaging apparatus which has hollow portions provided around each of color filters and achieves the prevention of the peeling of each of the color filters. The solid-state imaging apparatus having a plurality of light receiving portions provided on a semiconductor substrate includes: a plurality of color filters arranged correspondingly to each of the plurality of light receiving portions; and hollow portions formed around each of the plurality of color filters, wherein each of the color filters has one peripheral part contacting with adjacent one or more of the color filters.

Abstract: A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.

Abstract: Provided are a light emitting device, a light emitting device package, and a lighting system including the same. The light emitting device includes a second electrode layerelectrode, a light emitting structure, a texture, and a current spreading layer. The light emitting structure is on second electrode layerelectrode, and includes a second conductive type semiconductor layer, an active layer on the second conductive type semiconductor layer, and a first conductive type semiconductor layer on the active layer. The texture is on at least one portion of the light emitting structure. The current spreading layer is on the light emitting structure provided with the texture.

Abstract: A LED device is provided. The LED comprises a frame, a housing, a LED chip and a protection component. The frame comprises a first lead frame and a second lead frame disposed along a first direction and isolated from each other. The housing partially covers the first and second lead frames, and has a receiving portion exposing parts of the surfaces of the first and second lead frames. The LED chip is disposed in the receiving portion on the exposed surface of the first lead frame, and electrically connected to the first and second lead frames. The protection component is disposed on a surface of the second lead frame that is covered by the housing and electrically connected to the first lead frame. None of the sides of a vertical projection of the protection component on the second lead frame is parallel or perpendicular to the first direction.

Abstract: An integrated circuit structure includes a triple-axis accelerometer, which further includes a proof-mass formed of a semiconductor material; a first spring formed of the semiconductor material and connected to the proof-mass, wherein the first spring is configured to allow the proof-mass to move in a first direction in a plane; and a second spring formed of the semiconductor material and connected to the proof-mass. The second spring is configured to allow the proof-mass to move in a second direction in the plane and perpendicular to the first direction. The triple-axis accelerometer further includes a conductive capacitor plate including a portion directly over, and spaced apart from, the proof-mass, wherein the conductive capacitor plate and the proof-mass form a capacitor; an anchor electrode contacting a semiconductor region; and a transition region connecting the anchor electrode and the conductive capacitor plate, wherein the transition region is slanted.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.