Abstract: A display region E that includes an element isolation region 88 having a display region trench density D1, and in which a pixel circuit 110 including a transistor is arranged; a drive circuit region 105 that includes a region in which a drive circuit element isolation portion having a drive circuit region trench density D2 is provided, and in which drive circuits 101 and 102 that supply signals for driving the pixel circuit 110 are arranged; and a peripheral region 106 that includes region in which a peripheral element isolation portion having a peripheral region trench density D3 is provided, and is arranged at least between the display region E and the drive circuit region 105. The display region trench density D1 is different from the drive circuit region trench density D2, and the display region trench density D1 is equal to the peripheral region trench density D3.

Abstract: A display substrate, a method for fabricating the same and a display device are disclosed.

Abstract: An organic light emitting diode, including a first electrode; a first light emitting unit on the first electrode; a charge generating layer on the first light emitting unit, the charge generating layer including a plurality of organic layers; a second light emitting unit on the charge generating layer; and a second electrode on the second light emitting unit, the plurality of organic layers of the charge generating layer including a first organic layer and a second organic layer that are respectively adjacent to the first light emitting unit and the second light emitting unit; and a third organic layer between the first organic layer and the second organic layer, the first organic layer and the second organic layer being one of a p-type layer or a hole transport layer, and the third organic layer being the other of the p-type layer or the hole transport layer.

Abstract: A semiconductor ultraviolet light emitting device includes: a substrate; a buffer layer disposed on the substrate and comprising a plurality of nanorods between which a plurality of voids are formed; a first conductive nitride layer disposed on the buffer layer and having a first conductive AlGaN layer; an active layer disposed on the first conductive nitride layer and having a quantum well including AlxInyGa1-x-yN (0?x+y?1, 0?y<0.15); and a second conductive nitride layer disposed on the active layer and having a second conductive AlGaN layer, in which the plurality of nanorods satisfy 3.5?n(?)×D/??5.0, where ? represents a wavelength of light generated by the active layer, n(?) represents a refractive index of the plurality of nanorods at a wavelength of ?, and D represents diameters of the plurality of nanorods.

Abstract: A solar cell and a method for manufacturing the same are discussed. The solar cell may include a substrate, an emitter layer positioned at a first surface of the substrate, a first anti-reflection layer that is positioned on a surface of the emitter layer and may include a plurality of first contact lines exposing a portion of the emitter layer, a first electrode that is electrically connected to the emitter layer exposed through the plurality of first contact lines and may include a plating layer directly contacting the emitter layer, and a second electrode positioned on a second surface of the substrate.

Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

Abstract: The present invention provides an OLED display device, which includes: a substrate (1), a plurality of pixel zones arranged in an array on the substrate (1), each of the pixel zones comprising a pixel electrode (2), an organic light-emitting layer (3), and a common electrode (4) that are sequentially stacked on the substrate (1), and a pixel separation layer (5) including a plurality of openings, the openings being each delimited and circumferentially surrounded by a pixel separation layer sidewall (51), each of the openings corresponding to one of the pixel zones. The pixel separation layer (5) is formed of an inorganic material.

Abstract: A photo-detector having a photonic crystal structure for absorbing photons passing perpendicular to a surface of the photo-detector and a plasmonic resonance structure for absorbing photons passing along the surface of the photo-detector.

Abstract: A process for fabricating a LED lighting apparatus includes disposing a composite coating on a surface of a LED chip. The composite coating comprises a first composite layer having a manganese doped phosphor of formula I and a first binder, and a second composite layer comprising a second phosphor composition and a second binder. The first binder, the second binder or both include a poly(meth)acrylate. Ax[MFy]:Mn4+??(I) wherein A is Li, Na, K, Rb, Cs, or a combination thereof; M is Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Hf, Y, La, Nb, Ta, Bi, Gd, or a combination thereof; x is the absolute value of the charge of the [MFy] ion; y is 5, 6 or 7.

Abstract: Integrated circuits and methods of forming the same are provided. An exemplary method of forming an integrated circuit includes forming a dummy gate structure overlying a semiconductor substrate. The dummy gate structure includes a gate dielectric layer, a dummy gate layer, an etch stop layer, and a dummy gate cap layer. First sidewall spacers are formed adjacent to sidewalls of the dummy gate structure. A source and drain region are formed in the semiconductor substrate adjacent to the first sidewall spacers. A dielectric material is deposited adjacent to the first sidewall spacers. The dummy gate cap layer is etched with a first etchant selective thereto after depositing the dielectric material. The etch stop layer is etched with a second etchant that is selective thereto. The dummy gate layer is etched to form a gate recess, and a gate material is deposited in the gate recess.

Abstract: A method for producing a semiconducting organic film comprising the steps: preparing a first mixture comprising a first organic semiconducting material of type p having a molar mass of less than or equal to 2,000 g·mol?1 and a first organic semiconducting material of type n having a molar mass of less than or equal to 2,000 g·mol?1, adding a second organic semiconducting material to the first mixture to form a second mixture, wherein the second organic semiconducting material is one or more polymers having a molar mass greater than or equal to 10,000 g·mol?1, and forming the organic film from the second mixture.

Abstract: FinFET devices and methods of fabricating a FinFET device are provided. An exemplary method of fabricating a FinFET device includes providing a semiconductor substrate with a plurality of fins and a multi-layered hardmask stack formed thereover. The multi-layered hardmask stack is patterned to form a patterned multi-layered hardmask stack having a tapered fin masking configuration with a shortened region and an elongated region. A region of fins adjacent to the shortened region is masked with a second mask. The region of fins masked with the second mask is free from the patterned multi-layered hardmask stack. Fins in unmasked areas are etched after forming the second mask. The second mask is removed with at least one layer of the patterned multi-layered hardmask stack remaining after etching the fins in the unmasked areas. End portions of the fins adjacent to the shortened region are etched after removing the second mask.

Abstract: A second electrode (130) is superimposed on a first electrode (110). An organic layer (120) is positioned between the first electrode (110) and the second electrode (130). Furthermore, the organic layer (120) includes a light emitting layer (123). Furthermore, the organic layer (120) includes an alkali-containing layer (which is an electron transporting layer (125) in an example in the present drawing, and is hereinafter described as the electron transporting layer (125)) between the light emitting layer (123) and the second electrode (130). The electron transporting layer (125) includes an alkali metal. In the electron transporting layer (125), a content of the alkali metal as an elemental substance is greater than the content of a compound of the alkali metal.

Abstract: Provided is an array substrate for mounting a chip. The array substrate includes a plurality of conductive layers unidirectionally stacked with respect to an original chip substrate; a plurality of insulating layers alternately stacked with the plurality of conductive layers, and electrically separate the plurality of conductive layers; and a cavity having a groove of a predetermined depth with respect to a region including the plurality of insulating layers in an upper surface of the original chip substrate. Accordingly, since the optical device array of a single structure is used as a line source of light, an emission angle emitted from the optical device is great, it is not necessary to form an interval for supplying an amount of light, and a display device can be simply constructed. Further, since it is not necessary to perform soldering a plurality of LED packages on a printed circuit board, a thickness of a back light unit can be reduced.

Abstract: Disclosed is an integrated circuit comprising a substrate (10); and an optical CO2 sensor comprising: first and second light sensors (12, 12?) on said substrate, said second light sensor being spatially separated from the first light sensor; and a layer portion (14) including an organic compound comprising at least one amine or amidine functional group over the first light sensor; wherein said integrated circuit further comprises a signal processor (16) coupled to the first and second light sensor for determining a difference in the respective outputs of the first and second light sensor. An electronic device comprising such a sensor and a method of manufacturing such an IC are also disclosed.

Abstract: A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.

Abstract: A structure of micro-electro-mechanical systems (MEMS) electroacoustic transducer is disclosed. The MEMS electroacoustic transducer includes a substrate having a MEMS device region, a diaphragm having openings and disposed in the MEMS device region, a silicon material layer disposed on the diaphragm and sealing the diaphragm, and a conductive pattern disposed beneath the diaphragm in the MEMS device region. Preferably, a first cavity is also formed between the diaphragm and the substrate.

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

Abstract: A multilayered magnetic thin-film stack including a tunneling barrier layer; a magnetic finned layer formed on a first surface of the tunneling barrier layer; and a magnetic free layer formed on a second surface of the tunneling barrier layer, which is opposite to the first surface, wherein at least one of the magnetic finned layer and the magnetic free layer includes a FeZr alloy layer and a first magnetic layer having a (001) bcc structure between the FeZr alloy layer and the tunneling barrier layer.

Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.