Abstract: A method to process a 3D device, the method including: providing a first substrate including a first level including a first single crystal silicon layer and a plurality of first transistors; providing a second substrate including a second level including a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer; forming a plurality of third transistors including the third single crystal silicon layer; forming a plurality of metal layers interconnecting the plurality of third transistors; and then performing a hybrid bonding of the second level onto the first level.

Abstract: An organic light emitting display apparatus includes a substrate including a plurality of pixels. The organic light emitting display apparatus further includes a plurality of organic light emitting diodes on the substrate so as to correspond to the plurality of pixels. The plurality of pixels includes a first pixel, a second pixel, a third pixel, and a fourth pixel which emit different color light. Each of the plurality of organic light emitting diodes includes a first electrode, a light emitting portion on the first electrode and a second electrode on the light emitting portion. A thickness of the first electrode of the first pixel is different from a thickness of the first electrode of the second pixel, and the thickness of the first electrode of the second pixel is different from a thickness of the first electrode of the third pixel.

Abstract: A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

Abstract: The present disclosure provides a display panel including a first area including a plurality of first pixels, and a second area including a pixel area including a plurality of second pixels and a plurality of light-transmitting areas disposed between the plurality of second pixels. Each of the plurality of first pixels and the plurality of second pixels include a light emitting element, such as a light emitting diode, and the light emitting element includes an anode layer and a plurality of cathode layers. The plurality of cathode layers disposed in the second area can be disposed in areas except for the light-transmitting areas. Thus, light transmittance in the light-transmitting areas of the display device can be improved, and the reliability of the display device can be enhanced effectively.

Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.

Abstract: A photodetector comprising: a separation region that is provided in a semiconductor substrate and defines a pixel region; a hole accumulation region that is provided in the semiconductor substrate of the pixel region along a side surface of the separation region; a multiplication region that is provided in the semiconductor substrate of the pixel region and is configured by joining a first conductivity type region and a second conductivity type region from the surface side of the semiconductor substrate in the thickness direction of the semiconductor substrate; and an insulating region provided in the semiconductor substrate in a region between the multiplication region and the hole accumulation region, wherein a formation depth of the insulating region is larger than a formation depth of the first conductivity type region.

Abstract: In the field of photoelectric devices, a visible light detector is provided with high-photoresponse based on a TiO2/MoS2 heterojunction and a preparation method thereof. The detector, based on a back-gated field-effect transistor based on MoS2, includes a MoS2 channel, a TiO2 modification layer, a SiO2 dielectric layer, Au source/drain electrodes and a Si gate electrode, The TiO2 modification layer is modified on the surface of the MoS2 channel. By employing micromechanical exfoliation and site-specific transfer of electrodes, the method is intended to prepare a detector by constructing a back-gated few-layer field-effect transistor based on MoS2, depositing Ti on the channel surface, and natural oxidation.

Abstract: The present invention provides a method for preparing a gallium oxide semiconductor structure and a gallium oxide semiconductor structure obtained thereby.

Abstract: A display panel includes a substrate having a first area in which first pixels are disposed and a second area in which second pixels and a light-transmitting area disposed between the second pixels are disposed, and a polarizing plate disposed above the light-transmitting area and including a light-transmitting pattern having a light transmittance higher than that of the remaining area, wherein the substrate includes a high-transmission area having a higher light transmittance than the remaining portion in a position corresponding to the second area.

Abstract: A display device, includes: a substrate; a first thin film transistor and a second thin film transistor disposed on the substrate; a via insulating layer disposed on the substrate, wherein the via insulating layer includes a first contact hole and a second contact hole, wherein the first contact hole exposes a portion of the first thin film transistor, and the second contact hole exposes a portion of the second thin film transistor; a first pixel structure disposed on the via insulating layer, wherein the first pixel structure overlaps the first thin film transistor, and includes a first lower electrode; and a second pixel structure spaced apart from the first pixel structure, wherein the second pixel structure overlaps the second thin film transistor, and includes a second lower electrode having a shape different from a shape of the first lower electrode.

Abstract: Provided is a light-emitting device including a reflective layer including a plurality of nano-structures two-dimensionally disposed regularly and a low-refractive-index layer disposed adjacent to the plurality of nano-structures, a first electrode disposed on the reflective layer, an organic emission layer disposed on the first electrode, and a second electrode disposed on the organic emission layer, wherein each of the plurality of nano-structures includes a non-metallic material, and the low-refractive-index layer includes a dielectric material having a second refractive index lower than a first refractive index of the non-metallic material.

Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: Provided is a method of high-density pattern forming, which includes: providing a substrate; forming a hard mask layer on the substrate; forming a sacrificial layer on the hard mask layer; forming photoresists arranged at intervals on the sacrificial layer; etching the sacrificial layer to enable the sacrificial layer to form a mandrel corresponding to the photoresist one by one, wherein a cross-sectional size of the mandrel gradually decreases from an end of the mandrel away from the hard mask layer to an end close to the hard mask layer; forming an isolation layer on the mandrel; removing the isolation layer on the top of the mandrel, the isolation layer covering the hard mask layer, and the mandrel to form an isolation sidewall pattern; and transferring the isolation sidewall pattern to the hard mask layer.

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

Abstract: According to various embodiments, an electronic device may include a housing, a display disposed in an internal space of the housing and viewable from an outside and including a display area, and a camera module disposed under the display overlapping at least a part of the display area and not including an aperture structure, wherein the camera module includes a lens housing, a plurality of lenses disposed on the lens housing, and an image sensor disposed under the plurality of lenses, wherein the display includes a display panel and a light blocking member comprising a light blocking material and including a light transmission region disposed on an inside and/or an outside of the display panel overlapping at least parts of the plurality of lenses as viewed from above the display.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first semiconductor die comprising a first capacitor, and a second semiconductor die in contact with the first semiconductor die and comprises a diode. The first semiconductor die and the second semiconductor die are arranged along a first direction, and a diode is configured to direct electrons accumulated at the first capacitor to a ground.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: Provided is a display substrate including a first display region and at least one second display region, wherein light transmittance of the second display region is greater than light transmittance of the first display region. The second display region of the display substrate is provided with a light adjustment layer configured to adjust a light transmission effect of the second display region.

Abstract: A display apparatus includes a first substrate having a display area and a non-display area; a pixel array layer provided on the display area of the first substrate; and a second substrate provided on the pixel array layer and having first and second grooves at side edges of the second substrate, wherein the first and second grooves are respectively located at first and second bending areas to facilitate a curvature radius of the end portions of the display and achieve a zero bezel display.