Abstract: In a method for forming a barrier layer, the barrier layer is formed on a base layer having a three-dimensional structure before a dopant-containing layer is formed on the base layer. At this time, at least one of a film thickness, a film quality, and a film type of the barrier layer is controlled in a height direction of the three-dimensional structure by using an atomic layer deposition (ALD) process.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a fin positioned on the substrate, a gate structure positioned on the fin, a pair of source/drain regions positioned on two sides of the fin, a dielectric layer positioned above the drain region and adjacent to the gate structure, and a storage conductive layer positioned on the dielectric layer. The drain region, the dielectric layer and the storage conductive layer form a storage structure.

Abstract: Various examples are provided for magnetic tunnel junctions and applications thereof. In one example, a magnetic tunnel junction (MTJ) device includes a first ferromagnetic (FM) layer; a gadolinium oxide (GdOX) tunnel barrier disposed on the first ferromagnetic layer; and a second FM layer disposed on the GdOX tunnel barrier. In another example, a perpendicular MTJ (pMTJ) device includes a first layer including a magnetic material; a tunnel barrier disposed on the first layer to form the pMTJ; and a second layer including the magnetic material, the second layer disposed on the tunnel barrier.

Abstract: A magnetic field sensor structure includes a magnetoresistive sensor assembly and a transistor assembly. A dielectric layer is deposited on the transistor assembly. The dielectric layer includes a trench that exposes an interconnect of the transistor assembly. A damascene process is performed to form an ultra-thick metal (UTM) layer within the trench to create a first metal coil. The first metal coil is configured as a first reset component. Another dielectric layer is formed on the first metal coil. A flux guide is formed within the another dielectric layer. A second metal coil is formed over the another dielectric layer. The second metal coil is configured as a second reset component. The first reset component and the second reset component are configured as a reset mechanism, which is responsive to the transistor assembly and operable to magnetize the flux guide to a predetermined orientation.

Abstract: A wafer having on one side a device area with a plurality of devices is processed by providing a protective film and applying the protective film, for covering the devices on the wafer, to the one side of the wafer, so that a front surface of the protective film is in direct contact with the one side of the wafer. The protective film is heated during and/or after applying the protective film to the one side of the wafer, so that the protective film is attached to the one side of the wafer, and the side of the wafer opposite to the one side is processed. Further, the invention relates to a method of processing such a wafer in which a liquid adhesive is dispensed only onto a peripheral portion of a protective film and/or only onto a peripheral portion of the wafer.

Abstract: A substrate is formed to include a substrate base and a substrate extension. A photodiode contacts the substrate base. The substrate extension is adjacent the photodiode. An additional device contacts the substrate extension. A sidewall spacer contacts the photodiode and the substrate extension. The additional device includes conductive elements within the substrate extension adjacent the sidewall spacer.

Abstract: A detection device is provided and includes substrate; drive electrode provided on substrate; detection electrode provided on substrate and capacitively coupling with drive electrode; first thin film transistor connected to drive electrode and second thin film transistor connected to first thin film transistor, first insulating film and second insulating film both stacked on substrate, wherein first thin film transistor comprises first gate electrode and first semiconductor layer, second thin film transistor comprises second gate electrode and second semiconductor layer, first semiconductor layer and second semiconductor layer are in same layer and are located between first insulating film and second insulating film, first gate electrode opposes first semiconductor layer via first insulating film, second gate electrode opposes second semiconductor layer via second insulating film, and distance from first gate electrode to first semiconductor layer is greater than distance from second gate electrode to second

Abstract: A process includes providing electronic chips, the chips having been diced beforehand and each including a stack including a matrix-array of pixels, an interconnect layer, first layer, joining the electronic chips to a carrier substrate, so as to leave a spacing region between the chips; forming a redistribution layer having lateral ends extending into each spacing region; forming metal pillars on the lateral ends; moulding a material including first segments, facing the first layers, second segments which are separate from the first segments, and which extend around the metal pillars; the first and second segments being coplanar; applying a heat treatment, the formed material being chosen so that the stack is curved with a convex shape; the second segments remaining coplanar at the end.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an image sensor. The method includes forming a photodetector in a substrate. A lower interconnect portion of an interconnect structure is formed over the photodetector. A removal process is performed to define a first opening overlying the photodetector in the lower interconnect portion. A lower etch stop layer is formed lining the first opening. The lower etch stop layer has a U-shape in the first opening. An upper interconnect portion of the interconnect structure is formed over the lower etch stop layer. A light pipe structure is formed overlying the photodetector. The U-shape of the lower etch stop layer extends continuously along sidewalls and a bottom surface of the light pipe structure.

Abstract: A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer, wherein the formation of the plurality of scribe lines includes removing portions of the second wafer from the second surface towards the first surface to form a third surface between the first surface and the second surface, and the plurality of scribe lines protrudes from the third surface of the second wafer.

Abstract: A semiconductor chip is mounted to a chip mounting portion of a leadframe which further includes and one or more leads in the leadframe arranged facing the chip mounting portion. The lead lies in a first plane and the chip mounting portion lies in a second plane, the first plane and the second plane mutually offset with a gap therebetween. An electrical component (such as a capacitor) is arranged on the chip mounting portion and extends vertically between the first plane and the second plane.

Abstract: An image sensing chip package structure includes a chip, an adhesive loop and a light-transmissible substrate member. The chip includes an image sensing region. The adhesive loop is connected to the chip, and has an inner peripheral surface that defines a plurality of protrusions which surround the image sensing region of the chip. The light-transmissible substrate member is connected to the adhesive loop oppositely of the chip to cover the image sensing region of the chip. Methods of manufacturing the image sensing chip package structures are also provided.

Abstract: A semiconductor light receiving element includes a first semiconductor layer, a waveguide type photodiode structure, an optical waveguide structure, and a fourth semiconductor layer. The waveguide type photodiode structure is provided on the first semiconductor layer. The waveguide type photodiode structure includes an optical absorption layer, a second semiconductor layer, a multiplication layer, and a third semiconductor layer. The optical waveguide structure is provided on the first semiconductor layer. The optical waveguide structure includes an optical waveguiding core layer and a cladding layer. An end face of the waveguide type photodiode structure faces to an end face of the optical waveguide structure. The fourth semiconductor layer is located between the end face of the waveguide type photodiode structure and the end face of the optical waveguide structure. The fourth semiconductor layer contacts the multiplication layer at the end face of the waveguide type photodiode structure.

Abstract: The present disclosure provides a semiconductor memory structure. The semiconductor memory structure includes a substrate, a gate structure, a drain stressor and a source stressor. The gate structure is disposed in the substrate. Each of the source stressor and the drain stressor includes a strained part disposed in the substrate.

Abstract: Methods for forming a transition metal material on a substrate and thermal processing such metal containing material in a cluster processing system are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a two-dimensional transition metal dichalcogenide layer on a substrate in a first processing chamber disposed in a cluster processing system, thermally treating the two-dimensional transition metal dichalcogenide layer to form a treated metal layer in a second processing chamber disposed in the cluster processing system, and forming a capping layer on the treated metal layer in a third processing chamber disposed in the cluster processing system.

Abstract: The present application discloses a method for fabricating a semiconductor device with metal spacers. The method includes providing a substrate; forming a plurality of plugs above the substrate; forming a plurality of metal spacers above the plurality of plugs; and, forming a plurality of air gaps positioned between the plurality of plugs; wherein the step of forming wherein the plurality of metal spacers comprises forming a first set of metal spacers, forming a second set of metal spacers, forming a third set of metal spacers, and forming a fourth set of metal spacers; wherein the second set of metal spacers is formed between the first set of metal spacers and the third set of metal spacers, and the third set of metal spacers is formed between the second set of metal spacers and the fourth set of metal spacers.

Abstract: A mold including insulation layers and sacrificial layers is formed on a substrate. A channel hole is formed through the mold. A first deposition process is performed using a first precursor including silane and a second precursor including silane and a halogen element to form a first preliminary blocking layer on a sidewall of the channel hole. A second deposition process is performed using the first precursor to form a second preliminary blocking layer on the sidewall of the channel hole. The first and second preliminary blocking layers form a third preliminary blocking layer. An oxidation process is performed on the third preliminary blocking layer to transform the third preliminary blocking into a first blocking layer. A charge storage layer, a tunnel insulation layer, and a channel layer are formed on the first blocking layer. The sacrificial layer is replaced with a gate electrode.

Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode and a magnetic junction directly on the conductive layer. The magnetic junction further includes a pinning structure above the conductive layer, a fixed magnet above the pinning structure, a tunnel barrier on the fixed magnet, a free magnet on the tunnel barrier layer and a second electrode above the free magnet. The conductive layer including iridium and the pinning structure including iridium provide switching efficiency.

Abstract: A method of manufacturing a carrier for semiconductor device packaging is provided. The method includes forming a carrier having a plurality of plateau regions separated by a plurality of channels. The carrier is configured and arranged to support a plurality of semiconductor die during a packaging operation. The plurality of channels is filled with a material configured to control warpage of the carrier.

Abstract: A low temperature deposited (400° C. or less) dielectric passivation layer is formed on physically exposed surfaces of a material stack including a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode. A laser anneal is then performed to improve the physical and chemical properties of the low temperature deposited dielectric passivation layer, without negatively impacting the multilayered MTJ pillar.