Abstract: Vertical channel field effect transistors and methods of forming the same include forming one or more vertical channels on a bottom source/drain layer. A seed layer is deposited on horizontal surfaces around the one or more vertical channels. A metal gate is deposited on the seed layer. A top source/drain layer is deposited above the one or more vertical channels and the metal gate.

Abstract: An integrated circuit device, and a method of forming, including a semiconductor substrate, isolation regions extending into the semiconductor substrate, a semiconductor strip, and a semiconductor fin overlapping and joined to the semiconductor strip is provided. A first dielectric layer and a second dielectric layer are disposed on opposite sidewalls of the semiconductor strip. The integrated circuit device further includes a first conductive liner and a second conductive liner, wherein the semiconductor strip, the first dielectric layer, and the second dielectric layer are between the first conductive liner and the second conductive line. The first conductive liner and the second conductive liner are between, and in contact with, sidewalls of a first portion and a second portion of the isolation regions.

Abstract: One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a substrate and a first gate layer disposed on the active layer, where at least one of the first active layer and the first gate layer includes a first layer alignment structure; a first bounding layer disposed over the first device layer, the first bounding layer including an opening arranged to detectably expose the first layer alignment structure; and a second device layer disposed over the bounding layer including a second layer alignment structure, where the second layer alignment structure is substantially aligned to the first layer alignment structure through the opening.

Abstract: Trenched-bonding-dam devices and corresponding methods of manufacture are provided. A trenched-bonding-dam device includes a bonding dam structure positioned upon a top surface of a substrate. The bonding dam structure has a bottom surface attached to a top surface of the substrate, an inner dam surrounded by an outer dam, and a trench between the inner and outer dams. The device may further include an optics system including a lens and an adhesive positioned within a bonding region between a bottom surface of the optics system and a top surface of at least one of the inner and outer dams. The trench may be dimensioned to receive a portion of the excess adhesive flowing laterally out of the bonding region during bonding of the substrate to the optics system, laterally confining the excess adhesive and reducing lateral bleeding of the adhesive.

Abstract: In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.

Abstract: In an example, a memory cell may have an access gate, a control gate coupled to the access gate, a first dielectric stack below an upper surface of a semiconductor, above the access gate, and between a first portion of the control gate and the semiconductor, and a second dielectric stack below the access gate and the first dielectric stack and between a second portion of the control gate and the semiconductor. Each of the first and second dielectric stacks may store a charge.

Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

Abstract: A transistor includes a semiconductor substrate having an intrinsic active device, a first terminal, and a second terminal. The transistor also includes an interconnect structure formed of layers of dielectric material and electrically conductive material on the semiconductor substrate. The interconnect structure includes a pillar, a tap interconnect, and a shield structure positioned between the pillar and the tap interconnect formed from the electrically conductive material and extending through the dielectric material. The pillar contacts the first terminal and connects to a first runner. The tap interconnect contacts the second terminal and connects to a second runner. The shield structure includes a base segment, a first leg, and a second leg extending from opposing ends of the base segment, wherein the first and second legs extend from opposing ends of the base segment in a direction that is antiparallel to a length of the base segment.

Abstract: A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 ?m. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.

Abstract: A thin-film transistor (TFT) array substrate including at least one TFT, the at least one TFT including a semiconductor layer including a source region and a drain region having a first doping concentration on a substrate, a channel region between the source and drain regions and having a second doping concentration, the second doping concentration being lower than the first doping concentration, and a non-doping region extending from the source and drain regions; a gate insulating layer on the semiconductor layer; a gate electrode on the gate insulating layer and at least partially overlapping the channel region; and a source electrode and a drain electrode insulated from the gate electrode and electrically connected to the source region and the drain region, respectively.

Abstract: A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.

Abstract: A semiconductor integrated circuit includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type formed in an upper portion of the semiconductor substrate, a second well region of the first conductivity type formed in an upper portion of the first well region, an insulating layer formed separated from the first well region on a bottom portion of the semiconductor substrate that is directly beneath the first well region, and a rear surface electrode layer formed on a bottom of the insulating layer.

Abstract: Vertical channel field effect transistors include a bottom source/drain layer. One or more vertical channels are formed on the bottom source/drain layer. A horizontal seed layer is formed around the one or more vertical channels. A metal gate is formed directly on the seed layer. A top source/drain is formed layer above the one or more vertical channels and the metal gate.

Abstract: An antifuse device includes a gate structure formed on a substrate including first spacers formed in an upper portion and a conductive material formed in a lower portion below the first spacers. Two conductive regions are disposed adjacent to the gate structure and on opposite sides of the gate structure. A dielectric barrier is formed between the conductive material and each of the conductive regions such that a dual antifuse is formed across the dielectric barrier between the conductive material and the conductive regions on each side of the gate structure.

Abstract: According to one embodiment, the electrode films are stacked with gaps interposed between the electrode films. The first insulating film is provided between a lowermost electrode film of the electrode films and the substrate and being a metal oxide film, a silicon carbide film, or a silicon carbonitride film. The second insulating film is provided on an uppermost electrode film of the electrode films and being a metal oxide film, a silicon carbide film, or a silicon carbonitride film. The stacked film includes a semiconductor film extending in a stacking direction of the stacked body in the stacked body, and a charge storage film provided between the semiconductor film and the electrode films.

Abstract: Systems and methods are disclosed for capturing sound for communication by mounting one or more intra-oral microphones to capture sound; and mounting a mouth wearable communicator in the oral cavity to communicate sound with a remote unit.

Abstract: A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs.

Abstract: The semiconductor device includes a semiconductor element, and an electro-conductive first plate-like part electrically connected to a top-face-side electrode of the semiconductor element and including a first joint part projecting from a side face, and an electro-conductive second plate-like part including a second joint part projecting from a side face. A bottom face of the first joint part and a top face of the second joint part face one another, and are electrically connected via an electro-conductive bonding material. A bonding-material-thickness ensuring means is provided in a zone where the bottom face of the first joint part and the top face of the second joint part face one another to ensure a thickness of the electro-conductive bonding material between an upper portion of a front end of the second joint part and the bottom face of the first joint part.

Abstract: An electronic device is provided. The electronic device comprises a fin transistor formed over a substrate which is structured to include a device isolation region and an active region, the fin transistor including: a layer formed over the substrate and having a trench crossing the device isolation region and the active region; a gate filled in the trench; a first fin formed over and overlapping the active region and protruding over the device isolation region; and second fins formed on both sidewalls of the first fin in a direction of the trench.

Abstract: A method includes forming a diffusion barrier over a semiconductor structure. The formation of the diffusion barrier includes performing a first tantalum deposition process, the first tantalum deposition process forming a first tantalum layer over the semiconductor structure, performing a treatment of the first tantalum layer, and performing a second tantalum deposition process after the treatment of the first tantalum layer. The treatment modifies at least a portion of the first tantalum layer. The second tantalum deposition process forms a second tantalum layer over the first tantalum layer.