Abstract: Disclosed is a method of forming an integrated circuit (IC) structure with multiple non-planar transistors having different effective channel widths. In the method, sacrificial gates are removed from partially completed transistors, creating gate openings that expose sections of semiconductor fins between source/drain regions. Prior to forming replacement metal gates in the gate openings, additional process steps are performed so that, in the resulting IC structure, some transistors have different channel region heights and, thereby different effective channel widths, than others. These steps can include forming isolation regions in the bottoms of some gate openings. Additionally or alternatively, these steps can include filling some gate openings with a sacrificial material, recessing the sacrificial material to expose fin tops within those gate openings, either recessing the fin tops or forming isolation regions in the fin tops, and removing the sacrificial material.

Abstract: A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.

Abstract: A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first conductive plug and a second conductive plug over the semiconductor substrate and adjacent to each other. The semiconductor device structure includes a first conductive via structure and a second conductive via structure over the semiconductor substrate and adjacent to each other. A first distance between the first conductive plug and the second conductive plug is less than a second distance between the first conductive via structure and the second conductive via structure. A first height of the first conductive plug is greater than a second height of the first conductive via structure.

Abstract: A single-poly nonvolatile memory cell includes a coupling capacitor, a cell transistor and a selection transistor. The cell transistor has a floating gate, a first source, and a first drain. The floating gate is coupled to an array control gate/source line through the coupling capacitor. The first source is coupled to the array control gate/source line. The selection transistor has a selection gate, a second source, and a second drain. The selection gate is coupled to a word line. The second source is coupled to the first drain. The second drain is coupled to a bit line.

Abstract: The invention relates to a switching device for switching radio frequency signals. The switching devices comprises at least a first field effect transistor that comprises a first source node, a first gate node and a first drain node, wherein the first gate node is arranged between a first drain region and a first source region on a semiconductor substrate. The switching device comprises at least a second field effect transistor that comprises a second source node, a second gate node and a second drain node, wherein the second gate node is arranged between a second drain region and a second source region on the same semiconductor substrate. The first source region of the first transistor is directly connected to the second drain region of the second transistor to build a common node of the switching device. An input node and an output node of the switching device are directly connected to the common node.

Abstract: A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.

Abstract: A semiconductor device may include a first conductive pattern disposed in a first interlayer insulating film, a second conductive pattern disposed in a second interlayer insulating film positioned on the first interlayer insulating film, a through electrode partially penetrating through the first interlayer insulating film and the second interlayer insulating film. The through electrode electrically connects the first conductive pattern and the second conductive pattern. The device further includes a first pattern completely surrounding side surfaces of the through electrode, and a second pattern between the first pattern and the through electrode. The second pattern is separated from the first pattern and the through electrode. The device includes a third pattern connecting the first pattern and the second pattern.

Abstract: Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and capacitor electrically connected to the substrate. The capacitor includes a lower electrode, a dielectric layer disposed on the lower electrode, and an upper electrode disposed on the dielectric layer. The upper electrode includes a first electrode on the dielectric layer and a second electrode on the first electrode, such that the first electrode is disposed between the dielectric layer and the second electrode. The first electrode contains metal oxynitride having a formula of MxOyNz, in which an atomic ratio (y/x) of oxygen (O) to metallic element (M) is a value in the range from 0.5 to 2.

Abstract: According to an embodiment, a semiconductor memory device comprises a substrate, a plurality of first conductive layers, a memory columnar body, a first semiconductor layer, a second semiconductor layer and a contact. The plurality of first conductive layers are stacked upwardly of the substrate. The memory columnar body extends in a first direction intersecting an upper surface of the substrate and a side surface of the memory columnar body is covered by the first conductive layers. The first semiconductor layer is connected to a lower end of the memory columnar body and extends in a second direction intersecting the first direction. The second conductive layer is provided between the first semiconductor layer and the first conductive layers. The second conductive layer is connected to the memory columnar body and extending in the second direction. The contact is connected to the second conductive layer and extends in the first direction.

Abstract: In order to realize a silicon PUF of lower power consumption, a semiconductor device includes first and second MIS transistors of the same conductive type in off-state coupled in series, as a PUF element. The PUF element outputs a signal of high level or low level depending on the potential of a connection node of the first and the second MIS transistors. Preferably, the MIS transistors are fin-type FETs.

Abstract: Disclosed is an avalanche photodiode using a silicon nanowire, including a first silicon nanowire formed of silicon (Si), a first conductive region formed by doping one surface of the first silicon nanowire with a first dopant, and a second conductive region formed by doping one surface of the first silicon nanowire with a second dopant having a conductive type different from that of the first dopant so as to be arranged continuously in a longitudinal direction from the first conductive region, wherein, when the magnitude of a reverse voltage applied to both ends of the first silicon nanowire is equal to or greater than a preset breakdown voltage, avalanche multiplication of inner current occurs due to the incidence of light from the outside.

Abstract: A method for generating a non-volatile memory device may comprise: applying plasma for a preset time period to an exposed surface of a channel of a field effect transistor such that a plurality of charge-trapping sites are formed at the channel. The channel is comprised of a multi-layer structure of atomically thin two-dimensional sheets.

Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.

Abstract: A semiconductor package includes a flexible film substrate including a chip mounting region and a cut-line interposed between an inner region and an outer region of the flexible film substrate, the cut-line partially surrounding the inner region. The semiconductor package further includes first interconnection lines extending in the inner region from a first side of the chip mounting region towards an edge of the inner region of the flexible film substrate, and second interconnection lines extending in the outer region from a second side of the chip mounting region towards an edge of the outer region of the flexible film substrate. The edge of the inner region and the edge of the outer region are located on the first side of the semiconductor chip.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate and a plurality of pixels formed over the substrate. Each of the pixels comprises a first region configured to emit light and a second region configured to pass external light therethrough. The second regions of at least three adjacent ones of the pixels have different areas.

Abstract: A MEMS microphone component including at least one sound-pressure-sensitive diaphragm element is formed in the layer structure of the MEMS component, which spans an opening in the layer structure. The diaphragm element is attached via at least one column element in the central area of the opening to the layer structure of the component. The deflections of the diaphragm element are detected with the aid of at least one piezosensitive circuit element, which is implemented in the layer structure of the diaphragm element and is situated in the area of the attachment of the diaphragm element to the column element.

Abstract: A method to provide an isolation feature over a semiconductor structure is disclosed. The method includes forming a fin structure over a semiconductor substrate, forming an oxide layer over the fin structure, wherein forming the oxide layer includes performing a wet chemical oxidation process on the fin structure with a solvent mixture, forming a dielectric layer over the oxide layer, and forming at least one isolation feature over the semiconductor structure.

Abstract: Provided are a phosphor, a phosphor manufacturing method, and a white light emitting device. The phosphor is represented as a chemical formula of aMO-bAl2O3-cSi3N4, which uses light having a peak wavelength in a wavelength band of about 350 nm to about 480 nm as an excitation source to emit visible light having a peak wavelength in a wavelength band of about 480 nm to about 680 nm (where M is one kind or two kinds of elements selected from Mg, Ca, Sr, and Ba (0.2?a/(a+b)?0.9, 0.05?b/(b+c)?0.85, 0.4?c/(c+a)?0.9)).