Abstract: An electronic device includes a radiation-emitting component, a radiation-responsive component, or a combination thereof. In one embodiment, the electronic device includes a substrate and a first structure overlying the substrate. The electronic device also includes a second structure that includes a first layer, wherein the first layer has a first refractive index, and the first layer includes a first edge. The electronic device further includes a second layer overlying at least portions of the first structure and the second structure at the first edge. The second layer has a second refractive index that is lower than the first refractive index. In another embodiment, the first structure includes a layer having a perimeter and a pattern lying within the perimeter. The pattern extends at least partly though the first layer to define an opening with a first edge. In another embodiment, a process is used to form the electronic device.

Abstract: A method is disclosed for integrally forming at least one low voltage device and at least one high voltage device. According to the method, a first gate structure and a second gate structure are formed on a semiconductor substrate, wherein the first and second gate structures are isolated from one another. One or more first double diffused regions are formed adjacent to the first gate structure in the semiconductor substrate. One or more second double diffused regions are formed adjacent to the second gate structure in the semiconductor substrate. One or more first source/drain regions are formed within the first double diffused regions. One or more second source/drain regions are formed within the second double diffused regions. The first double diffused regions function as one or more lightly doped source/drain regions for the low voltage device.

Abstract: A non-volatile memory array including memory units which are arranged in a row/column array is provided. Source lines are arranged in parallel in the column direction and connect to the source regions of the memory units in the same column. Bit lines are arranged in parallel in the row direction and connect to the drain regions of the memory units in the same row. Word lines are arranged in parallel in the column direction and connect to the select gates of the memory units in the same column. Control lines are arranged in parallel in the column direction and connect to the control gates of the memory units in the same column. The control lines are grouped into several groups with n control lines (n is a positive integer not less than 2) in one group, and the control lines in each group are electrically connected to each other.

Abstract: A high withstand voltage lateral semiconductor device capable of improving its on-state breakdown voltage and safe operation area (SOA) without lowering its current capabilities, and structured so as to be easy to produce.

Abstract: A semiconductor integrated circuit device includes a semiconductor region of a first conductivity type. A first insulated-gate field effect transistor having a source/drain region of a second conductivity type connected to an output terminal is formed on the semiconductor region. Further, a semiconductor region of a second conductivity type connected to the gate of the transistor is formed adjacent to the source/drain region of the transistor on the semiconductor region.

Abstract: A trench-gate semiconductor device (100) has a trench network (STR1, ITR1) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR1) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR1) adjacent corners of the transistor cells. As shown in FIG. 16 which is a section view along the line II-II of FIG. 11, the intersection trench regions (ITR1) each include insulating material (21D) which extends from the bottom of the intersection trench region with a thickness which is greater than the thickness of the insulating material (21B1) at the bottom of the segment trench regions (STR1). The greater thickness of the insulating material (21D) extending from the bottom of the intersection trench regions (ITR1) is effective to increase the drain-source reverse breakdown voltage of the device (100).

Abstract: The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.

Abstract: There are provided a metal I/O ring structure for a semiconductor chip and a decoupling capacitance structure using the same. In the Metal I/O ring structure, a plurality of first metal lines are formed on a first metal layer and connected with a power supply voltage, and a plurality of second metal lines are formed on the first metal layer and connected with a ground voltage. The second metal lines are arranged neighboring to the first metal lines. The second metal lines are connected with a second metal layer disposed below the first metal lines on the metal layer, and the first metal lines are connected with the second metal layer disposed below the second metal lines on the first metal layer. An insulating layer is disposed between the first metal layer and the second metal layer, thereby forming a decoupling capacitance between the first metal lines and the second metal lines.

Abstract: A barrier implanted region of a first conductivity type located below an isolation region of a pixel sensor cell and spaced from a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The barrier implanted region is formed by conducting a plurality of deep implants at different energies and doping levels below the isolation region. The deep implants reduce surface leakage and dark current and increase the capacitance of the photodiode by acting as a reflective barrier to electrons generated by light in the doped region of the second conductivity type of the photodiode.

Abstract: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Abstract: A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The carbon-doped silicon formed in the recesses resides close to the transistor channel and serves to provide a tensile stress to the channel, thereby facilitating improved carrier mobility in NMOS type transistor devices.

Abstract: A silicon-on-insulator (SOI) substrate including laminated layers of a substrate, an oxide layer, and a silicon layer in order. The oxide layer has an electrifying hole fluidly connected with the substrate and the electrifying hole is filled with a part of the silicon layer. A method for fabricating the floating structure is also disclosed which includes the steps of forming an oxide layer having a predetermined thickness on a substrate, forming one or more electrifying holes in an area of the oxide layer corresponding to an inner part of the floating structure, forming a silicon layer on the oxide layer including an electrification structure electrically connecting the silicon layer to the substrate, forming a pattern for the floating structure on the silicon layer, removing the oxide layer corresponding to an inner area of the pattern, forming a thermal oxide layer on a surface of the silicon layer, and removing the thermal oxide layer to form the floating structure.

Abstract: An integrated photosensitive device with a metal-insulator-semiconductor (MIS) photodiode constructed with one or more substantially continuous layers of semiconductor material and with a substantially continuous layer of dielectric material.

Abstract: A semiconductor product having a test structure, in which a contact connection short-circuits that source/drain region of a transistor which is connected to an inner capacitor electrode of a trench capacitor by a dopant diffusion region with an interconnect is disclosed. Methods are disclosed for making an electrical measurement, to determine the nonreactive resistance of dopant diffusion regions, the so-called “buried straps”, without the measurement result being corrupted by the nonreactive resistance of a transistor channel. In accordance with one embodiment of the invention having a plurality of electrical connections of the capacitor electrode, static currents can also be conducted through a buried strap and the capacitor electrode. Embodiments are disclosed that make it possible to perform at novel test structures of a semiconductor wafer electrical resistance measurements, which cannot be carried out at memory cells of a memory cell array themselves.

Abstract: Methods and solutions for forming self assembled organic monolayers that are covalently bound to metal interfaces are presented along with a device containing a self assembled organic monolayer. Embodiments of the present invention utilize self assembled thiolate monolayers to prevent the electromigration and surface diffusion of copper atoms while minimizing the resistance of the interconnect lines. Self assembled thiolate monolayers are used to cap the copper interconnect lines and chemically hold the copper atoms at the top of the lines in place, thus preventing surface diffusion. The use of self assembled thiolate monolayers minimizes the resistance of copper interconnect lines because only a single monolayer of approximately 10 ? and 20 ? in thickness is used.

Abstract: In the case of using an analog buffer circuit, an input voltage is required to be added a voltage equal to a voltage between the gate and source of a polycrystalline silicon TFT; therefore, a power supply voltage is increased, thus a power consumption is increased with heat. In view of the foregoing problem, the invention provides a depletion mode polycrystalline silicon TFT as a polycrystalline silicon TFT used in an analog buffer circuit such as a source follower circuit. The depletion mode polycrystalline silicon TFT has a threshold voltage on its negative voltage side; therefore, an input voltage does not have to be increased as described above. As a result, a power supply voltage requires no increase, thus a low power consumption of a liquid crystal display device in particular can be realized.

Abstract: A solid-state imaging device is formed on a silicon substrate for providing a MOS type solid-state imaging device which has a device isolation structure and causes a small amount of leak current. The solid-state imaging device includes, for each pixel, an imaging region which includes a photodiode having a charge accumulation region of a first conductivity type, a transistor and a device isolation region whose depth is less than a depth of the charge accumulation region of the first conductivity type, at which an impurity density is at maximum.

Abstract: A circuit structure for a package substrate or a circuit board is provided. The circuit structure has a dielectric layer with an upper surface and a lower surface, at least a first line and at least a second line. The first line is disposed on the dielectric layer on which a base of the first line is aligned with the upper surface. In addition, the second line is disposed on the dielectric layer on which a base of the second line is embedded below the upper surface. Since the second line is embedded into the dielectric layer, the distance with a reference plane is reduced and the crosstalk between the signals is further effectively reduced.

Abstract: Silicon oxide etching solutions containing the product of at least one bifluoride source compound dissolved in a solvent consisting of at least one carboxylic acid, and further comprising from about 0.5 to about 3 percent by solution weight of hydrofluoric acid and from about 1 to about 5 percent by solution weight of water, wherein the total concentration of bifluoride source compound is between about 1.25 and about 5.0 moles per kilogram of solvent. Methods for selectively removing silicon oxides and metal silicates from metal surfaces are also disclosed.

Abstract: A semiconductor device structure includes a passivation layer through which only non-silicon-comprising structures are exposed. The semiconductor device structure is formed by selectively forming the passivation layer on an exposed silicon-comprising surface by exposing surfaces of the semiconductor device to a liquid phase solution supersaturated in silicon dioxide. The exposure is conducted at substantially atmospheric temperature and pressure and achieves an effective passivation layer in an abbreviated time, and without subsequent heat treatment. A wafer that includes a back side coated with such a passivation layer may be subjected to a high-speed electroless process for plating the bond pad with a solder-enhancing material. The semiconductor device structure may also include via holes and microvia holes with walls that are passivated.