Abstract: Systems and methods for providing a storage extension system and method for secure and seamless access by various boot architectures are described. In some embodiments, an Information Handling System (IHS) may include a processor and a BIOS coupled to the processor, the BIOS having program instructions that, upon execution, cause the IHS to receive a request to access a bios storage region of the IHS from a driver, determine whether the device associated with the driver is a platform boot device such that when the boot device is a platform boot device, facilitate access to a native bios storage region of the bios storage region by the driver, and when the boot device is not a platform boot device, facilitate access to an extended bios storage region of the bios storage region by the driver.

Abstract: An information processing method includes, when an electronic apparatus is booted, obtaining current parameter information of a target hard disk drive and sending the current parameter information to a baseboard management controller (BMC). The current parameter information of the target hard disk drive indicates current mounting position of the target hard disk drive on a backplane (BP).

Abstract: Mechanisms for managing output of an HDMI source are provided. In accordance with some implementations of the disclosed subject matter, a method for controlling output of an HDMI source is provided, the method comprising: establishing a connection between the HDMI source and an HDMI sink at a first address of a consumer electronic control bus of the HDMI sink; sending a request for an identity of the active source connected to the HDMI sink; monitoring signals on the consumer electronic control bus; receiving a message over the consumer electronic control bus identifying a second address on the consumer electronic control bus different from the first address as an address of an active source; setting a status of the HDMI source as inactive in response to receiving the message; and inhibiting output of video from the HDMI source to the HDMI sink in response to the status being set as inactive.

Abstract: A storage device for booting a host computing device includes a first storage memory region having a first storage memory controller, a second storage memory region having a second storage memory controller, and a resilient boot controller. The resilient boot controller is configured to store boot code in the first storage memory region, prevent write access by the host computing device through the first storage memory controller to the first storage memory region, detect a reset of the host computing device through the input/output interface, copy at least a portion of the boot code from the first storage memory region to the second storage memory region, responsive to detection of the reset of the host computing device, and enable read access of the copied boot code by the host computing device through the second storage memory controller of the second storage memory region, responsive to the copy operation.

Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.

Abstract: Certain examples disclose and describe apparatus and methods to reprogram all electronic engine control system processors through a single external network interface to an aircraft data loader. In such examples, a main processor that interfaces to an aircraft communication network is to operate as both a data loader and a loadable device. Distributed electronic engine control processors are reprogrammable from a single network interface, rather than requiring separate, direct access to each controller.

Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

Abstract: An integrated circuit is presented. The integrated circuit has a set of sensor input interfaces and an output interface. The integrated circuit further has a memory with a first and second memory locations. The integrated circuit further has a multi-chip hub module which has a transaction buffer with both a real-time and a non-real-time buffer. The multi-chip hub module has a context mapper, a re-formatter module and an error handling module. The context mapper is configured to map data to the first or second memory location. The multi-chip hub module is configured to process data through the modules and provide processed data to the output interface.

Abstract: A processing device receives a command to arm a memory device for self-destruction. In response to the command, a self-destruction countdown timer is commenced. An expiry of the self-destruction countdown timer and based on detecting the expiry of the self-destruction countdown timer, data stored by the memory device is destructed.

Abstract: A storage controller communicates with a non-volatile memory device, and an operation method of the storage controller includes determining whether a first read voltage is registered at a history table, when it is determined that the first read voltage is registered at the history table, performing a first direct memory access (DMA) read operation on data stored in the non-volatile memory device, based on the first read voltage, obtaining a page count value, based on the first DMA read operation, determining a second read voltage different from the first read voltage based on a difference between the page count value and an idle count value, without an additional read operation for the data stored in the non-volatile memory device, and updating the first read voltage of the history table based on the second read voltage.

Abstract: A first command associated with a first memory die is communicated via a first portion of an interface of the memory sub-system. A second command associated with a second memory die is communicated via the first portion of the interface to a second memory die. A data burst corresponding to the first memory die is caused to be communicated via a second portion of the interface, where the second command is communicated via the first portion of the interface concurrently with the data burst communicated via the second portion of the interface.

Abstract: A system and method for determining optimal computing configuration for executing a computing operation includes defining one or more constrains of a given computing operation to be executed. The method further includes implementing a knowledge graph to determine at least one suitable combination of computing hardware and computing software based on the given computing operation and the defined one or more constrains therefor. The method further includes quantitatively estimating an energy requirement and qualitatively estimating an energy consumption pattern of the determined at least one suitable combination.

Abstract: A system includes a data storage device and a host computing device. The data storage device includes a host interface; integrated circuit memory cells; and a processing device. The processing device is configured to execute firmware to perform operations requested by commands received via the host interface and maintenance operations identified by the processing device independent of commands received via the host interface. The host computing device is coupled to the host interface to provide commands with addresses to access the integrated circuit memory cells according to the address. In response to a request, the host computing device is configured to reduce, to below a threshold, a rate of transmitting to the host interface commands to access integrated circuit memory cells; and power up the data storage device to cause the data storage device to perform the maintenance operations.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

Abstract: A chassis front-end is disclosed. The chassis front-end may include a switchboard including an Ethernet switch, a Baseboard Management Controller, and a mid-plane connector. The chassis front-end may also include a mid-plane including at least one storage device connector and a speed logic to inform at least one storage device of an Ethernet speed of the chassis front-end. The Ethernet speeds may vary.

Abstract: A method and apparatus for controlling startup of a hard disk drive system, and a storage device. The hard disk drive system includes two or more hard disk drives. The method for controlling startup of a hard disk drive system includes: latching the initialization states of all the hard disk drives after all hard disk drives are powered on; dividing all hard disk drives into two or more hard drive groups, each hard drive group includes more than one hard disk drive; sequentially perform link initialization negotiation on each hard drive group by using a port protocol; and in an OOB negotiation process of the link initialization negotiation, by setting the state of an SCSI application layer power state machine, control a motor of each hard disk drive in the hard drive group to enter a spinning state.

Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.

Abstract: According to one embodiment, a memory system is capable of being connected to a host. The memory system includes a nonvolatile memory and a controller that receives information regarding an operating state of the host. The controller controls the nonvolatile memory according to commands from the host and selects a parameter for interrupt coalescing for transmissions to the host of interrupts related to command completion notices for the commands from the host based on the information regarding the operating state of the host.

Abstract: A method of managing configurations of a plurality of system services, including a first system service and a second system service, in each of a plurality of hosts, wherein each of the hosts is configured with a virtualization software for supporting execution of virtual machines therein includes steps of: upon receiving an application programming interface (API) call to apply configurations of the system services defined in a desired configuration file to the system services, parsing the desired configuration file to identify a first configuration for the first system service and a second configuration for the second system service, and storing the first and second configurations in accordance with a configuration schema defined for the first and second system services, wherein the first system service executes with the stored first configuration applied thereto and the second system service executes with the stored second configuration applied thereto.

Abstract: An operating method of an electronic device including controllers includes updating, by a first-level controller of the controllers, a first-level firmware of the the first-level controller, writing, by the first-level controller, a second-level firmware to one of second-level controllers of the controllers having a lower level than the first-level controller, booting, by the one of the second-level controllers, by performing a reset operation, verifying, by the first-level controller or the booted second-level controller, whether there is a target second-level controller with out-of-date firmware, and writing, by the first-level controller or the booted second-level controller in response to a result of the verifying, the second-level firmware to the target second-level controller.