Patents Examined by Tammara R. Peyton
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Patent number: 11775462Abstract: An adaptive interface storage device. In some embodiments, the adaptive interface storage device includes: a rear storage interface connector; an adaptable circuit connected to the rear storage interface connector; a first multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the first multiplexer. The adaptive interface storage device may be configured to operate in a first state or in a second state. The adaptive interface storage device may be configured: in the first state, to present a device side storage interface according to a first storage protocol at the front storage interface connector, and in the second state, to present a device side storage interface according to a second storage protocol, different from the first storage protocol, at the front storage interface connector.Type: GrantFiled: January 22, 2021Date of Patent: October 3, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Stephen G. Fischer, Sompong Paul Olarig
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Patent number: 11775325Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.Type: GrantFiled: November 4, 2021Date of Patent: October 3, 2023Assignee: Dynavisor, Inc.Inventor: Sreekumar R. Nair
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Patent number: 11775316Abstract: A method is implemented by a system on chip and includes: receiving a volume attaching request sent by the public cloud management component, where the volume attaching request includes an identifier of a system volume; and storing the identifier of the system volume based on the volume attaching request, where when the bare-metal server is started, the bare-metal server uses the identifier of the system volume to determine the system volume, and starts an operating system of the bare-metal server based on the system volume, and the system volume stores a file used for starting the operating system of the bare-metal server.Type: GrantFiled: January 15, 2020Date of Patent: October 3, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Junjie Wang, Yijian Dong, Haitao Guo
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Patent number: 11768601Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n?1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.Type: GrantFiled: June 9, 2021Date of Patent: September 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Ramdas P. Kachare, Vijay Balakrishnan, Stephen G. Fischer, Fred Worley, Anahita Shayesteh, Zvi Guz
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Patent number: 11768793Abstract: A plug-in mobile peripheral component interconnect express module connector is disclosed, comprising a plastic body, and a first terminal set and a second terminal set disposed relatively in the plastic body. The plastic body includes transversely penetrated slots, an upper end surface of the slots has intermittently plural upper magazines, and a lower end surface has intermittently plural lower magazines. The first terminal set includes plural first elastic terminals inserted in the upper magazines, and the second terminal set includes plural second elastic terminals inserted in the lower magazines. Each first elastic terminal is opposed to each second elastic terminal, forming a holding gap. A motherboard is inserted between the first elastic terminals and the second elastic terminals from a side, and an MXM board is inserted between the first elastic terminals and the second elastic terminals from the other side.Type: GrantFiled: May 21, 2021Date of Patent: September 26, 2023Assignee: DUN-PU ELECTRONICS CO. LTD.Inventor: Huang-Wen Wang
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Patent number: 11762584Abstract: Techniques facilitating write-only device state inferences. In one example, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise: a monitor component; and a state component. The monitor component can compare a property of a feedback signal output by a write-only device with a reference signal. The state component can determine a state of the write-only device based on a comparison between the property and the reference signal.Type: GrantFiled: October 22, 2020Date of Patent: September 19, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jarrett Betke, George Russell Zettles, IV, Jeremy T. Ekman, Austin Carter
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Patent number: 11762789Abstract: An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.Type: GrantFiled: January 31, 2022Date of Patent: September 19, 2023Assignee: PROTEANTECS LTD.Inventors: Eyal Fayneh, Evelyn Landman, Shai Cohen, Guy Redler, Inbar Weintrob
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Patent number: 11748111Abstract: An address range mirroring system includes a plurality of processing subsystem/memory subsystem nodes that each include a respective processing subsystem coupled to a respective memory subsystem, an operating system provided by at least one of the plurality of processing subsystem/memory subsystem nodes, and a Basic Input/Output System (BIOS) that is coupled to the plurality of processing subsystem/memory subsystem nodes. The BIOS identifies an address range mirroring memory size that was provided by the operating system, and an address range mirroring node usage identification that was provided by the operating system. The BIOS then configures address range mirroring according to the address range mirroring memory size in the respective memory subsystem in each of a subset of the plurality of processing subsystem/memory subsystem nodes, with the subset of the plurality of processing subsystem/memory subsystem nodes based on the address range mirroring node usage identification.Type: GrantFiled: January 31, 2022Date of Patent: September 5, 2023Assignee: Dell Products L.P.Inventors: Ching-Lung Chao, Shih-Hao Wang
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Patent number: 11748115Abstract: A system could include persistent storage containing application components. A plurality of software applications could be installed on the system. The software applications could be respectively associated context records that include references to application components that provide some behavior or data for the software applications. The system could also include processors configured to perform operations. The operations could include receiving a request to generate a topology map for a software application and identifying, based on a context record for the software application, a subset of application components that provide some behavior or data for the software application. The operations could further include determining relationship types between pairs of application components and generating a topology map for the software application.Type: GrantFiled: July 21, 2020Date of Patent: September 5, 2023Assignee: ServiceNow, Inc.Inventors: Jacob Burman, Michel Abou Samah, Kylin Follenweider, Sharon Elizabeth Carmichael Ehlert
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Patent number: 11733917Abstract: A PCIe architecture is disclosed incorporating a controller memory buffer (CMB). Write data is written to the CMB and is not read out for processing upon receiving a write command for the write data. The data is read out of the CMB and processed to obtain processed data upon receiving feedback from a NAND channel controller. The processed data may be written directly to the NAND channel controller or may be written to a light write buffer that is read by the NAND channel controller. The processed data may be written to a light write buffer functioning as a cut through buffer.Type: GrantFiled: September 17, 2020Date of Patent: August 22, 2023Assignee: PETAIO INC.Inventors: Yimin Chen, Fan Yang
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Patent number: 11726926Abstract: Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes a processor and the docking station includes a high-performance processor. The method includes determining a docking state of a dockable device while at least an application is running. Application migration from the dockable device to a docking station is initiated when the dockable device is moving to a docked state. Application migration from the docking station to the dockable device is initiated when the dockable device is moving to an undocked state. The application continues to run during the application migration from the dockable device to the docking station or during the application migration from the docking station to the dockable device.Type: GrantFiled: December 6, 2021Date of Patent: August 15, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Jonathan Lawrence Campbell, Yuping Shen
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Patent number: 11720449Abstract: A computer-implemented method at a data management system comprises; retrieving start and end times of a backup of a database; retrieving time stamps of log backups of the database; retrieving sequence numbers of the log backups; generating a graphical user interface illustrating a timeline of availability of database restoration and unavailability; making a second backup of the database; illustrating, on the graphical user interface during the making, pending availability of the second database backup; receiving a command to restore the database at an available time as illustrated by the graphical user interface; and restoring the database.Type: GrantFiled: November 3, 2021Date of Patent: August 8, 2023Assignee: Rubrik, Inc.Inventors: Deepti Kochar, Snehal Arvind Khandkar, Kevin Rui Luo, Yanzhe Wang
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Patent number: 11720265Abstract: In some implementations, a computing device may configure a new device based on a current state of an old device, including settings, preferences, and other user data. The data may be transferred from the old device to the new device, and then relocated according to a manifest that details positions of the data on the old device. The destination device may be rebooted into a configuration mode to allow for the relocation of the transferred data, and then rebooted again to configure the destination device to provide access to the data in its respective relative locations on the destination device.Type: GrantFiled: October 29, 2021Date of Patent: August 8, 2023Assignee: Apple Inc.Inventors: Jean-Pierre Ciudad, George C. Chicioreanu, Yan Arrouye
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Patent number: 11720264Abstract: One or more storage systems are connected to one or more storage boxes comprising multiple storage devices. Multiple storage areas provided by one or more storage boxes include an allocated area, which is a storage area that is allocated to a virtual volume, and an empty area, which is a storage area that is not allocated to any logical volume. Multiple owner rights corresponding to multiple storage areas are set in one or more storage systems. A storage system having an empty area owner right changes an empty area to the allocated area by allocating the empty area. In a case where a configuration change (a relative change in the number of storage boxes with respect to the number of storage systems) is performed, a first storage system that exists after the configuration change sets, in the first storage system, either more or fewer owner rights than the owner rights, which have been allocated to the first storage system before the configuration change.Type: GrantFiled: May 7, 2021Date of Patent: August 8, 2023Assignee: Hitachi, Ltd.Inventors: Akira Yamamoto, Miho Imazaki
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Patent number: 11720369Abstract: Techniques are provided for path management and failure prediction in a multipath environment using target port power levels. One method comprises obtaining, by a first entity that communicates with a second entity via multiple paths, a transmit power level and/or a receive power level of a target port associated with the second entity; evaluating the transmit power level and/or the receive power level of the target port relative to a threshold; and setting, by the first entity, a path state of one or more paths between the first entity and the target port to a standby state based on the evaluating, wherein the first entity establishes paths between the first entity and one or more other target ports of the second entity in an active state. Existing communications on the one or more paths between the first entity and the target port may be allowed to complete in the standby state.Type: GrantFiled: October 13, 2020Date of Patent: August 8, 2023Assignee: EMC IP Holding Company LLCInventors: Joseph G. Kanjirathinkal, Peniel Charles, Owen Crowley
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Patent number: 11714656Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller. The controller controls the nonvolatile memory. The nonvolatile memory includes a first area where specific software is capable of being stored, and a second area where the specific software is stored. The second area has higher reliability than the first area. The controller causes the specific software to be stored in the first area when receiving a command specifying the specific software, and executes loading of the specific software stored in the first area at startup of the controller.Type: GrantFiled: September 8, 2020Date of Patent: August 1, 2023Assignee: Kioxia CorporationInventor: Yoshihiro Takanashi
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Patent number: 11709605Abstract: A processing device in a memory system receives requests to perform a plurality of memory access operations at a memory device configured with a zone namespace having a plurality of zones, the memory device comprising a plurality of planes, wherein each zone of the plurality of zones is associated with a respective plane of the plurality of planes. The processing device further concurrently performs the plurality of memory access operations on data stored in different zones of the plurality of zones, wherein the different zones are associated with different planes of the plurality of planes.Type: GrantFiled: September 13, 2021Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventor: Luca Bert
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Patent number: 11693805Abstract: An adaptive memory expansion scheme is proposed, where one or more memory expansion capable Hosts or Accelerators can have their memory mapped to one or more memory expansion devices. The embodiments below describe discovery, configuration, and mapping schemes that allow independent SCM implementations and CPU-Host implementations to match their memory expansion capabilities. As a result, a memory expansion host (e.g., a memory controller in a CPU or an Accelerator) can declare multiple logical memory expansion pools, each with a unique capacity. These logical memory pools can be matched to physical memory in the SCM cards using windows in a global address map. These windows represent shared memory for the Home Agents (HAs) (e.g., the Host) and the Slave Agent (SAs) (e.g., the memory expansion device).Type: GrantFiled: July 12, 2021Date of Patent: July 4, 2023Assignee: XILINX, INC.Inventors: Jaideep Dastidar, Millind Mittal
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Patent number: 11690955Abstract: Disclosed is a method of controlling operation of a medical device that regulates delivery of a fluid medication to a user. The method obtains a current sensor-generated value that is indicative of a physiological characteristic of the user, and is produced in response to operation of a continuous analyte sensor device. The method continues by: calculating a sensor quality metric that indicates reliability and trustworthiness of the current sensor-generated value; adjusting, in response to the calculated sensor quality metric, therapy actions of the medical device to configure a quality-specific operating mode of the medical device; managing generation of user alerts at the medical device in response to the calculated sensor quality metric; and regulating delivery of the fluid medication from the medical device, in accordance with the current sensor-generated value and the quality-specific operating mode of the medical device.Type: GrantFiled: April 23, 2020Date of Patent: July 4, 2023Assignee: MEDTRONIC MINIMED, INC.Inventors: Louis J. Lintereur, Alexander S. Campbell, Dmytro Y. Sokolovskyy, Neha J. Parikh, Maria Diana Miller
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Patent number: 11687285Abstract: A processing device in a memory system receives a request to read data stored on a first plane of a plurality of planes of a memory device while a plurality of write operations are ongoing, wherein each of the plurality of write operations are performed concurrently to write each of a plurality of single-plane segments of data to a corresponding plane of the plurality of planes of the memory device, and wherein a multi-plane segment of data received with a write request is divided into the plurality of single-plane segments of data. The processing device further suspends a first write operation of the plurality of write operations, the first write operation corresponding to the first plane, and performs a read operation to read the data stored on the first plane while continuing to perform at least one other write operation of the plurality of write operations corresponding to another plane of the plurality planes.Type: GrantFiled: September 13, 2021Date of Patent: June 27, 2023Assignee: Micron Technology, Inc.Inventor: Luca Bert