Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.

Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.

Abstract: A processing device in a memory system receives, from a host system, a host-resident translation layer read command comprising a physical address of data to be read from a memory device, wherein the physical address is indicated in at least a portion of a translation layer entry previously provided to the host system with a response to a host-resident translation layer write command and stored in a host-resident translation layer mapping table. The processing device further performs a read operation to read the data stored at the physical address from the memory device and sends, to the host system, the data from the physical address of the memory device.

Abstract: Examples are described that relate to waking up or invoking a function such as a processor-executed application or a hardware device. The application or a hardware device can specify which sources can cause wake-ups and which sources are not to cause wake-ups. A device or processor-executed software can monitor reads from or writes to a region of memory and cause the application or a hardware device to wake-up unless the wake-up is specified as inhibited. The updated region of memory can be precisely specified to allow a pinpoint retrieval of updated content instead of scanning a memory range for changes. In some cases, a write to a region of memory can include various parameters that are to be used by the woken-up application or a hardware device. Parameters can include a source of a wake-up, a timer to cap execution time, or any other information.

Abstract: The disclosure describes wireless communication systems. The wireless communication system includes first memory, second memory, a direct memory access (DMA) controller, an encryption engine in-line between the DMA controller and the second memory, a first microprocessor, and a second microprocessor. The first microprocessor communicates with other systems that generate application data to be wirelessly transmitted. The application data to be wirelessly transmitted is stored in the second memory and programs the DMA controller to transfer packets of the application data to the first memory from the second memory. The encryption engine receives the packets of the application data from the DMA controller, encrypts the packets to generate encrypted application data packets, and outputs the encrypted application data packets for storage to the first memory.

Abstract: A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.

Abstract: A tablet computer is provided, which includes a sensor section operable to detect positional input by a human operator and output a positional input signal; a display, laid over the sensor section, operable to receive and display a video signal; and a processor, coupled to a memory storing programs for running an operating system (OS) and executing software loaded to the memory, the processor being operable to receive and process the positional input signal from the sensor section and to output a video signal of the OS and the software to the display. The tablet computer further includes a sensor signal filter capable of selectively communicating the positional input signal from the sensor section to the processor, to a separate external processor, or to neither the processor nor the separate external processor; and a display switch capable of coupling the display to the processor or to the separate external processor.

Abstract: Techniques related to temporary setpoint values are disclosed. The techniques may involve causing operation of a fluid delivery device in a first mode for automatically delivering fluid to a patient based on a first target glucose value. Additionally, the techniques may involve obtaining a second target glucose value. The second target glucose value may be a temporary target glucose value to be used for a specified period of time to regulate fluid delivery to the patient, and the second target glucose value may be greater than the first target glucose value. The techniques may further involve causing, based on obtaining the second target glucose value, operation of the fluid delivery device in a second mode for automatically delivering fluid to the patient. The second mode may be for reduced fluid delivery during the specified period of time.

Abstract: A Key-Value (KV) storage device is disclosed. The KV storage device may include storage for objects, each object including data associated with a key. A host interface layer may receive requests to read data associated with a key from the storage, to write data associated with a key to the storage, and a boot request to get boot data from the storage. A boot request processor may process the boot request using the storage.

Abstract: Systems, apparatuses, and methods related to a domain register of a processor in a computer system are described. The computer system has a memory configured to at least store instructions of routines that are classified in multiple predefined, non-hierarchical domains. The processor stores in the domain register an identifier of a current domain of a routine that is being executed in the processor. The processor is configured to perform security operations based on the content of the domain register and the security settings specified respectively for the predefined, non-hierarchical domains.

Abstract: Apparatus and methods of providing digital varying output, such as sinusoidal, pulse width modulation, SPWM, control for an inverter comprising at least a first switch and a second switch are disclosed. The method comprising: generating a first binary control signal at a system modulation frequency; generating a second binary control signal at an M-times higher carrier frequency; wherein generating the second binary control signal comprises: providing a periodic counter having a K-times higher reset frequency; calculating M switch-off moments; determining for each, a corresponding switch-off counter value and a corresponding counter sequence value; storing each switch-off counter value in a respective memory location corresponding to the respective counter sequence and dummy values in the remaining memory locations; and sequentially and periodically transferring the contents of the memory locations to at least one PWM value register.

Abstract: In part, the disclosure relates to systems and methods to rapidly copy the computer operating system, drivers and applications from a source computer to a target computer using a duplication engine. Once the copy is complete the source computer will resume execution, and the target computer will first alter its configuration (also referred to as a role or personality) and then resume execution conforming to its new configuration as indicated by a profile stored in protected or specialized memory. The profile can be value, a file, or other memory structure and is protected in the sense that the profile (and or the region of memory where it is stored) must not be overwritten by a state transfer from the source computer to the target computer.

Abstract: Methods and systems are disclosed for treating a person with diabetes by basal rate adjustment of insulin from a therapy delivery device based on risk associated with a glucose state of the person with diabetes. A method may include determining a current risk metric associated with a detected glucose state. The method may include determining a current risk metric associated with the detected glucose state based on a weighted average of cumulative hazard values of return paths generated from a glucose state distribution around a detected glucose state. The method may include calculating an adjustment to a basal rate of a therapy delivery device based on the current risk metric associated with the detected glucose state and a reference risk metric associated with a reference glucose level.

Abstract: Disclosed is a method of controlling operation of a medical device that regulates delivery of a fluid medication to a user. The method receives meter-generated values that are indicative of a physiological characteristic of the user, and are produced in response to operation of an analyte meter device. The method obtains sensor-generated values that are indicative of the physiological characteristic of the user, and are produced in response to operation of a continuous analyte sensor device, different than the analyte meter device. The medical device is operated in different modes when: a valid meter-generated value is available; a valid meter-generated value is unavailable and a current sensor-generated value satisfies first quality criteria; or a valid meter-generated value is unavailable and the current sensor-generated value satisfies second quality criteria but does not satisfy the first quality criteria.

Abstract: A memory sub-system includes a memory sub-system controller comprising at least one host channel, a memory device comprising a plurality of memory die, and at least one input/output (I/O) expander circuit coupled between the at least one host channel of the memory sub-system controller and to the memory device to connect the plurality of memory die to the memory sub-system controller. The at least one I/O expander circuit is to limit an impedance load presented on the at least one host channel to an impedance load of a corresponding subset of the plurality of memory die selected during a given time period.

Abstract: A technology for controlling non-volatile memory with a multi-stage controller is shown. The multi-stage controller uses an upper on-chip interconnect and a lower on-chip interconnect and includes a serial peripheral bus (SPI) loader, a frond-end central processing unit (FE CPU), and an arbitrator. When being connected to the lower on-chip interconnect, the SPI loader performs code loading for the multi-stage controller. After the SPI loader finishes the code loading, the SPI loader is disconnected from the lower-stage on-chip bus, and the arbitrator connects the FE CPU to the lower on-chip interconnect. This way, the communication channel between the upper on-chip interconnect and the lower on-chip interconnect is not occupied by the FE CPU.

Abstract: Provided is a disaggregated memory server, which in some examples is a rack-mounted hardware appliance comprising a pool of memory for allocation to memory clients. Examples of memory clients may include one or more rack-mounted computing devices co-located on a rack with the disaggregated memory server. The disaggregated memory server may be optimized for high-speed dynamic memory allocation to the other computing devices in the rack.

Abstract: A data storage management layer comprises computing device(s), operatively connected to storage resources, which comprise data storage units and control units. The data storage management layer is operatively connected to the storage resources. They are operatively connected to host computers. A sub-set of the storage resources are assigned to each host, in order to provide storage services according to performance requirements predefined for the host, thereby generating Virtual Private Arrays (VPA). The computing device(s) are configured to perform a method of managing the data storage system comprising: (a) implement storage management strategies, comprising rules. The rules comprise conditions and actions. The actions are capable of improving VPA performance in a dynamic manner; (b) repetitively performing: (i) monitor VPA performance for detection of compliance of VPA with the condition(s); and (ii) responsive to detection of compliance of VPA with the condition(s), performing the action(s).

Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing security settings for calls from predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a call to execute a routine identified using the virtual memory address, a security setting corresponding to the execution domain from which the call initiates can be extracted from the page table entry to determine whether a security measure is to be used. For example, a shadow stack structure can be used to protect the private stack content of the routine from being access by a caller and/or to protect the private stack content of the caller from being access by the callee.

Abstract: Methods that boot a secondary operating system (O/S) kernel with reclaimed primary kernel memory are disclosed herein. One method includes booting, via a processor performing a boot algorithm, a secondary kernel for an O/S in response to a primary kernel for the O/S going offline, in which the secondary kernel is configured to be loaded to a reserved memory area. The method further includes reclaiming memory space from the primary kernel for use in booting the secondary kernel in response to a determination that the reserved memory area includes insufficient memory space for completing the boot algorithm. Also disclosed herein are apparatus, systems, and computer program products that can include, perform, and/or implement the methods for providing a secondary kernel that includes a reserved area in memory.