Abstract: According to one embodiment, a memory system is capable of being connected to a host. The memory system includes a nonvolatile memory and a controller that receives information regarding an operating state of the host. The controller controls the nonvolatile memory according to commands from the host and selects a parameter for interrupt coalescing for transmissions to the host of interrupts related to command completion notices for the commands from the host based on the information regarding the operating state of the host.

Abstract: A method of managing configurations of a plurality of system services, including a first system service and a second system service, in each of a plurality of hosts, wherein each of the hosts is configured with a virtualization software for supporting execution of virtual machines therein includes steps of: upon receiving an application programming interface (API) call to apply configurations of the system services defined in a desired configuration file to the system services, parsing the desired configuration file to identify a first configuration for the first system service and a second configuration for the second system service, and storing the first and second configurations in accordance with a configuration schema defined for the first and second system services, wherein the first system service executes with the stored first configuration applied thereto and the second system service executes with the stored second configuration applied thereto.

Abstract: An operating method of an electronic device including controllers includes updating, by a first-level controller of the controllers, a first-level firmware of the the first-level controller, writing, by the first-level controller, a second-level firmware to one of second-level controllers of the controllers having a lower level than the first-level controller, booting, by the one of the second-level controllers, by performing a reset operation, verifying, by the first-level controller or the booted second-level controller, whether there is a target second-level controller with out-of-date firmware, and writing, by the first-level controller or the booted second-level controller in response to a result of the verifying, the second-level firmware to the target second-level controller.

Abstract: In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

Abstract: The present disclosure relates to a Flash memory component having a structurally independent structure and coupled to a System-on-Chip through a plurality of interconnection pads, comprising: a memory array including a plurality of independently addressable sub arrays; sense amplifiers coupled to corresponding outputs of said sub arrays and coupled to a communication channel of said System-on-Chip; a scan-chain comprising modified JTAG cells coupled in parallel between the output of the sense amplifiers and said communication channel to allow performing read operations in a Direct Memory Access.

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

Abstract: Methods, systems, and devices for automotive boot optimization are described. For instance, a memory system may record addresses that are accessed as part of multiple phases of a first boot-up procedure. During a second boot-up procedure, the memory system may transfer, from a logical block address of a non-volatile memory device to a volatile memory device, information for a respective phase based on the recording of the phases of the first boot-up procedure. The memory system may receive a command to transmit the information to a host system as part of the respective phase after transferring the information from the non-volatile device to the volatile memory device.

Abstract: A boot method for an embedded system is provided. The embedded system includes two mainboards each provided with a baseboard management controller (BMC), a non-volatile memory unit and a network adapter. When the embedded system is turned on, each of the BMCs performs a boot procedure, and then loads an operating system (OS) image file from a corresponding non-volatile memory unit to execute an operating system. When one BMC fails to load the OS image file or to execute the operating system, the BMC causes the corresponding network adapter to communicate with the other network adapter to acquire the OS image file from the non-volatile memory unit on the other mainboard, so as to replace the OS image file in the corresponding non-volatile memory unit, and directly loads the OS image thus acquired to execute the operating system.

Abstract: Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.

Abstract: Waveform circuitry and related apparatuses and methods are disclosed. An apparatus includes a memory device to store waveform data corresponding to a waveform, a processor, and a waveform circuitry to autonomously pre-process the waveform data independently from the processor and provide the pre-processed waveform data to one or more peripheral devices. A pre-processed waveform corresponding to the pre-processed waveform is data different from the waveform.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more methods may: execute a first information handling system (IHS) initialization executable via an environment associated with IHS firmware; register, by the first IHS initialization executable, a process configured to store multiple IHS initialization executable/OS executable pairs via a volatile memory medium of the IHS; for each IHS initialization executable/OS executable pair of the multiple IHS initialization executable/OS executable pairs: call, by an IHS initialization executable of the IHS initialization executable/OS executable pair, the process; and copy, by the process, an OS executable of the IHS initialization executable/OS executable pair from the first non-volatile memory medium to the volatile memory medium; retrieve a driver via a network; execute the driver; and copy, by the driver, each OS executable, which was copied to the volatile memory medium, to a non-volatile memory medium of the IHS.

Abstract: A clustered storage system includes a plurality of storage devices, each of which contributes a portion of its memory to form a global cache of the clustered storage system that is accessible by the plurality of storage devices. Cache metadata for accessing the global cache may be organized in a multi-layered structure. In one embodiment, multi-layered structure has a first layer first including a first address array, and the first address array include addresses pointing to a plurality of second address arrays in a second layer. Each second address array in the second layer includes addresses, each of which points to data that has been cached in the global cache.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: A method of providing more efficient and streamlined data access to DRAM storage medium by all of multiple processors within a system on a chip (SoC) requires every processor to send use-of-bus request. When the request is for local access (that is, for access to that part of DRAM which is reserved for that processor), the processor reads or writes to the DRAM storage medium through its own arbitrator and own memory controller. When the request is for non-local access (that is, to DRAM within the storage medium which is reserved for another processor), the processor reads or writes to the “foreign” address in the storage medium through its own arbiter, its own memory controller, and its own DMA controller. A data access system is also disclosed.

Abstract: Systems, apparatuses, and methods related to image based media type selection are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile). Determinations of which memory media types to write image data to can be made and the data can be written (e.g., stored) in the determined type of memory media. A determined memory media type can be based on attributes of the data. In an example, a method can include receiving, by a memory system that comprises a plurality of memory media types, initial image data from an image sensor coupled to the memory system, identifying one or more attributes of the initial image data, determining a type of memory media to write the initial image data to based on the identified attributes of the initial image data , and selecting, based at least in part on the determined type of memory media, a first memory type of the plurality of memory media types to write the initial image data.

Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

Abstract: A computer-implemented method according to one embodiment includes receiving, on a first cluster site, a first I/O request to migrate a plurality of filesets from a second cluster site to the first cluster site. The first cluster site includes a plurality of gateway nodes. The method further includes identifying at least two of the gateway nodes having resources available to perform operations of the migration, and hashing information of a plurality of filesets against the identified gateway nodes. The information includes inode numbers of entities that are mounted during fulfillment of the first I/O request. Operations of the first I/O request are distributed to the identified gateway nodes based on the hashing, and the identified gateway nodes are instructed to fulfill the operations.

Abstract: A medical system includes an input assembly for receiving one or more user inputs. The input assembly includes at least one slider assembly for providing an input signal. Processing logic receives the input signal from the input assembly and provides a first output signal and a second output signal. A display assembly is configured to receive, at least in part, the first output signal from the processing logic and render information viewable by the user. The second output signal is provided to one or more medical system components. The information rendered on the display assembly may be manipulatable by the user and at least a portion of the information rendered may be magnified.

Abstract: A content provider system includes: a repository to store a catalog of content; a storage device pool to load content from among the catalog of content from the repository into one or more storage devices of the storage device pool; a first hosted device communicably connected to the storage device pool, and to execute the content stored in the storage device pool to provide the content to a first user device; a second hosted device communicably connected to the storage device pool, and to execute the content stored in the storage device pool to provide the content to a second user device; and one or more processing circuits to identify an available storage device from among the one or more storage devices of the storage device pool for serving a requested content to a requesting device from among the first and second hosted devices.