Abstract: A MEMS device formed by a substrate, having a surface; a MEMS structure arranged on the surface; a first coating region having a first Young's modulus, surrounding the MEMS structure at the top and at the sides and in contact with the surface of the substrate; and a second coating region having a second Young's modulus, surrounding the first coating region at the top and at the sides and in contact with the surface of the substrate. The first Young's modulus is higher than the second Young's modulus.

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

Abstract: A semiconductor device includes a gate electrode structure, a channel, first division patterns, and a second division pattern. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each gate electrode extends in a second direction parallel to the substrate. The channel extends in the first direction through the gate electrode structure. The first division patterns are spaced apart from each other in the second direction, and each first division pattern extends in the second direction through the gate electrode structure. The second division pattern is between the first division patterns, and the second division pattern and the first division patterns together divide a first gate electrode in a third direction parallel to the substrate and crossing the second direction. The second division pattern has an outer contour that is a curve in a plan view.

Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

Abstract: A semiconductor device according to the present embodiment includes a circuit board comprising a plurality of electrodes provided on a first surface, a first resin layer provided on the first surface around the electrodes, and a second resin layer provided on the first resin layer. A first semiconductor chip is connected to a first one of the electrodes. A second semiconductor chip is provided above the first semiconductor chip, being larger than the first semiconductor chip, and is connected to a second one of the electrodes via a metal wire. A third resin layer is provided between the first semiconductor chip and the second semiconductor chip and between the second resin layer and the second semiconductor chip, and covers the first semiconductor chip.

Abstract: A vertical memory device includes a plurality of word lines on a substrate, a plurality of word line cut regions extending parallel to each other, a memory cell array comprising a plurality of channel structures extending on the substrate through the plurality of word lines and arranged in a honeycomb structure, a plurality of contacts on the plurality of channel structures, and a plurality of bit lines connected to the plurality of channel structures through the plurality of contacts. The memory cell array comprises a first sub-array and a second sub-array, which are defined by the plurality of word line cut regions and are connected to some identical bit lines from among the plurality of bit lines, and a layout of contacts in the first sub-array from among the plurality of contacts is different from a layout of contacts in the second sub-array from among the plurality of contacts.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.

Abstract: A method for fabricating a vertical memory device includes: forming a memory cell array that includes a vertical thyristor and a word line over a first substrate; forming a peripheral circuit unit in a second substrate; bonding the memory cell array with the peripheral circuit unit; removing the first substrate to expose one side of the vertical thyristor; and forming a bit line that is coupled to the one side of the vertical thyristor and the peripheral circuit unit.

Abstract: A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

Abstract: In a solid-state imaging device, a material forming an underfill part is prevented from flowing toward a side of a pixel region, shortening of a distance between an end portion of an opening of a substrate and the pixel region is enabled, and miniaturization is promoted. The device includes: an imaging element having a pixel region including a large number of pixels on one plate surface of a semiconductor substrate; a substrate provided on the surface side with respect to the imaging element and having an opening for passing light to be received by the pixel region; and an underfill part including a cured fluid and covering a connection part that electrically connects the imaging element and the substrate, in which the substrate has a groove for guiding the fluid forming the underfill part in a direction away from the surface of the imaging element.

Abstract: A semiconductor element bonding structure capable of strongly bonding a semiconductor element and an object to be bonded and relaxing thermal stress caused by a difference in thermal expansion, by interposing metal particles and Ni between the semiconductor element and the object to be bonded, the metal particles having a lower hardness than Ni and having a micro-sized particle diameter. A plurality of metal particles 5 (aluminum (Al), for example) having a lower hardness than nickel (Ni) and having a micro-sized particle diameter are interposed between a semiconductor chip 3 and a substrate 2 to be bonded to the semiconductor chip 3, and the metal particles 5 are fixedly bonded by the nickel (Ni). Optionally, aluminum (Al) or an aluminum alloy (Al alloy) is used as the metal particles 5, and aluminum (Al) or an aluminum alloy (Al alloy) is used on the surface of the semiconductor chip 3 and/or the surface of the substrate 2.

Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.

Abstract: An organic light emitting diode display device includes a substrate, first and second active patterns, and first and second sub-pixel structures. The substrate has a first sub-pixel circuit region including a first driving transistor region and a second sub-pixel circuit region including a second driving transistor region. The first active pattern is disposed in the first sub-pixel circuit region and has a first bent portion in the first driving transistor region. The second active pattern is disposed in the second sub-pixel circuit region and has a second bent portion in the second driving transistor region. In a direction in a plan surface, the first active pattern has a first recess formed by the first bent portion, and the second active pattern has a second recess formed by the second bent portion. An area of the second recess is less than that of the first recess.

Abstract: The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 ?m pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.

Abstract: The present invention provides a semiconductor package structure including a first dielectric layer, an integrated chip, a second power chip, a first patterned conductive layer, a second patterned conductive layer, a first conductive adhesive part, a second conductive adhesive part, a plurality of first conductive connecting elements and a plurality of second conductive connecting elements, and including a build-up circuit structure below, wherein the integrated chip includes a control chip and a first power chip. By means of integrating the control chip and the first power chip into a single chip, volume of semiconductor package structure can be further reduced. In addition, a manufacturing method of a semiconductor package structure is also provided.

Abstract: A display device includes a first electrode disposed on a substrate, a second electrode disposed on the substrate and spaced apart from the first electrode, at least one light-emitting element extending in a direction, disposed between the first electrode and the second electrode, and electrically connected to the first electrode and the second electrode, and an insulating pattern layer disposed on the first electrode and the second electrode, the insulating pattern layer including a fixer disposed on at least part of the at least one light-emitting element, and a barrier surrounding the at least one light-emitting element.

Abstract: Provided is a display device. The display device includes: a substrate; a gate line disposed on the substrate; a transistor including a part of the gate line; and a light-emitting element connected to the transistor, in which the gate line includes a first layer including aluminum or an aluminum alloy, a second layer including titanium nitride, and a third layer including metallic titanium nitride. An N/Ti molar ratio of the metallic titanium nitride may be in a range from about 0.2 to about 0.75.

Abstract: A display panel having a display region and a non-display region, the display panel includes: a substrate having at least one first opening; an electronic component disposed on the substrate; a plurality of pads disposed in the non-display region and including a first pad and a second pad are spaced apart from each other in a first direction with the at least one first opening therebetween; and an adhesive layer disposed between the substrate and the electronic component and overlapping the at least one first opening.