Patents Examined by Telly D Green
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Patent number: 11769700Abstract: A semiconductor substrate including an upper surface and a lower surface may include a bump pad unit disposed on the upper surface. The semiconductor substrate may also include test pads disposed on the upper surface or the lower surface. The semiconductor substrate may also include traces configured to connect the bump pad unit and the test pads. The bump pad unit includes a main bump pad disposed on the upper surface, and a plurality of side bump pads disposed on the upper surface to be spaced apart from the main bump pad. The traces may connect the main bump pad and the plurality of side bump pads to the test pads in a one-to-one manner.Type: GrantFiled: August 19, 2020Date of Patent: September 26, 2023Assignee: SK hynix Inc.Inventor: Bok Gyu Min
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Patent number: 11770950Abstract: The invention relates to a light extraction substrate having a light extraction layer. The light extraction layer includes boron, boroate, and/or borosilicate as well as nanoparticles.Type: GrantFiled: December 27, 2021Date of Patent: September 26, 2023Assignee: Vitro Flat Glass LLCInventors: Cheng-Hung Hung, James W. McCamy
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Patent number: 11764183Abstract: Provided is a joint structure interposed between a semiconductor element and a substrate, the joint structure including: a Sn phase; Cu alloy particles containing P in an amount of 1 mass % or more and less than 7 mass %; and Ag particles, wherein the Cu alloy particles are each coated with a Cu6Sn5 layer, wherein the Ag particles are each coated with a Ag3Sn layer, wherein the Cu alloy particles and the Ag particles are at least partially bonded to each other through a Cu10Sn3 phase, wherein a total of addition amounts of the Cu alloy particles and the Ag particles is 25 mass % or more and less than 65 mass % with respect to the joint structure, and wherein a mass ratio of the addition amount of the Ag particles to the addition amount of the Cu alloy particles is 0.2 or more and less than 1.2.Type: GrantFiled: November 8, 2018Date of Patent: September 19, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Koji Yamazaki, Yoshio Tamura
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Patent number: 11756944Abstract: A semiconductor wafer includes unit regions that are repeatedly arranged, and each unit region of the unit regions includes: at least one first chip region; and at least one second chip region spaced apart from the at least one first chip region by a scribe line, wherein a first area size of each of the at least one first chip region is different from a second area size of each of the at least one second chip region from a planar viewpoint.Type: GrantFiled: September 17, 2020Date of Patent: September 12, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-Bum Kim, Sung Hoon Kim, Dae Seok Byeon
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Patent number: 11756624Abstract: Methods of forming a transistor might include forming a dielectric overlying a semiconductor having a first conductivity type, forming a conductor overlying the dielectric, patterning the conductor and dielectric to define a gate stack of the transistor, forming a first extension region base and a second extension region base in the semiconductor, forming a first extension region riser overlying the first extension region base and forming a second extension region riser overlying the second extension region base, and forming a first source/drain region in the first extension region riser and forming a second source/drain region in the second extension region riser, wherein the first extension region base, the second extension region base, the first source/drain region, and the second source/drain region each have a second conductivity type different than the first conductivity type.Type: GrantFiled: March 3, 2022Date of Patent: September 12, 2023Inventor: Haitao Liu
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Patent number: 11749662Abstract: A semiconductor package includes: a first semiconductor chip including a plurality of front surface pads disposed on a first active surface of a first semiconductor substrate, at least one penetrating electrode penetrating at least a portion of the first semiconductor substrate and connected to the front surface pads, a first rear surface cover layer disposed on a first inactive surface of the first semiconductor substrate, a first rear surface dummy conductive layer penetrating a portion of the first rear surface cover layer; a second semiconductor chip including a second front surface cover layer disposed on a second active surface of a second semiconductor substrate, and a second front surface dummy conductive layer penetrating a portion of the second front surface cover layer; and at least one first bonded pad penetrating the first rear surface cover layer and the second front surface cover layer.Type: GrantFiled: October 19, 2021Date of Patent: September 5, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangcheon Park, Youngmin Lee
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Patent number: 11742319Abstract: A method of manufacturing an electronic device is disclosed. An electronic unit is provided. The electronic unit has a chip and at least one bonding pin. The electronic unit is mounted on the substrate through the at least one bonding pin, and an adhesive material is applied to a space between the chip and the substrate.Type: GrantFiled: September 23, 2021Date of Patent: August 29, 2023Assignee: InnoLux CorporationInventors: Yi-An Chen, Wan-Ling Huang, Tsau-Hua Hsieh
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Patent number: 11742430Abstract: The invention allows stable fabrication of a TFT circuit board used in a display device and having thereon an oxide semiconductor TFT. A TFT circuit board includes a TFT that includes an oxide semiconductor. The TFT has a gate insulating film formed on part of the oxide semiconductor and a gate electrode formed on the gate insulating film. A portion of the oxide semiconductor that is covered with the gate electrode 104 and a portion of the oxide semiconductor that is not covered with the gate electrode are both covered with a first interlayer insulating film. The first interlayer insulating film is covered with a first film 106, and the first film is covered with a first AlO film.Type: GrantFiled: June 15, 2021Date of Patent: August 29, 2023Assignee: Japan Display Inc.Inventors: Yohei Yamaguchi, Kazufumi Watabe, Tomoyuki Ariyoshi, Osamu Karikome, Ryohei Takaya
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Patent number: 11742395Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.Type: GrantFiled: March 28, 2022Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yi Lee, Ya-Huei Li, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 11737319Abstract: A display apparatus includes: a substrate including a display area and a sensor area, wherein the display area includes a first pixel, and the sensor area includes a second pixel and a transmission portion; a sensor configured to transmit a signal through the substrate via the transmission portion, wherein the second pixel includes second thin-film transistor including a semiconductor layer, and wherein a blocking layer is disposed between the sensor and the second thin-film transistor, wherein the blocking layer covers the semiconductor layer.Type: GrantFiled: February 4, 2022Date of Patent: August 22, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Injun Bae, Chulho Kim, Yunhwan Park, Jin Jeon, Beohmrock Choi
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Patent number: 11735575Abstract: Interconnecting a first chip and a second chip by a bridge member includes a chip handler for handling the first chip and the second chip. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The chip handler has an opening and at least one support surface for supporting the first surfaces of the first chip and the second chip when the first chip and the second chip are mounted to the chip handler. A chip support member supports the first chip and the second chip from the second surfaces, and a bridge handler is provided for inserting the bridge member through the opening of the chip handler and for placing the bridge member onto the first sets of terminals of the first chip and the second chip.Type: GrantFiled: May 27, 2021Date of Patent: August 22, 2023Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Takahito Watanabe, Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori
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Patent number: 11730007Abstract: To provide a light-emitting element which uses a fluorescent material as a light-emitting substance and has higher luminous efficiency. To provide a light-emitting element which includes a mixture of a thermally activated delayed fluorescent substance and a fluorescent material. By making the emission spectrum of the thermally activated delayed fluorescent substance overlap with an absorption band on the longest wavelength side in absorption by the fluorescent material in an S1 level of the fluorescent material, energy at an S1 level of the thermally activated delayed fluorescent substance can be transferred to the S1 of the fluorescent material. Alternatively, it is also possible that the S1 of the thermally activated delayed fluorescent substance is generated from part of the energy of a T1 level of the thermally activated delayed fluorescent substance, and is transferred to the S1 of the fluorescent material.Type: GrantFiled: June 1, 2022Date of Patent: August 15, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Seo, Hiromi Seo, Tatsuyoshi Takahashi
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Patent number: 11715637Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.Type: GrantFiled: February 2, 2022Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu Ling Liao, Chung-Chi Ko, Wan-Yi Kao
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Patent number: 11715729Abstract: A display module and a method for manufacturing thereof are provided. The display module includes a glass substrate; a thin film transistor (TFT) layer provided on a surface of the glass substrate, the TFT layer including a plurality of TFT electrode pads; a plurality of light emitting diodes (LEDs) provided on the TFT layer, each of the plurality of LEDs including LED electrode pads that are electrically connected to respective TFT electrode pads among the plurality of TFT electrode pads; and a light shielding member provided on the TFT layer and between the plurality of LEDs, wherein a height of the light shielding member with respect to the TFT layer is lower than a height of the plurality of LEDs with respect to the TFT layer.Type: GrantFiled: April 29, 2021Date of Patent: August 1, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yoonsuk Lee, Eunhye Kim, Sangmoo Park, Dongyeob Lee
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Patent number: 11710646Abstract: A fan-out packaging method includes: prepare circuit patterns on one side or both sides of a substrate; install electronic parts on one side or both sides of the substrate; prepare packaging layers on both sides of the substrate; the packaging layers on both sides of the substrate package the substrate, the circuit patterns, and the electronic parts, the packaging layers being made of a thermal-plastic material; wherein the substrate is provided with a via hole; both sides of the substrate are communicated by means of the via hole; a part of the packaging layers penetrate through the via hole when the packaging layers are prepared on both sides of the substrate; and the packaging layers on both sides of the substrate are connected by means of the via hole.Type: GrantFiled: October 11, 2018Date of Patent: July 25, 2023Assignee: SHENZHEN XIUYI INVESTMENT DEVELOPMENT PARTNERSHIP (LIMITED PARTNERSHIP)Inventors: Chuan Hu, Yingqiang Yan, Yuejin Guo, Yingjun Pi, Junjun Liu, Edward Prack
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Patent number: 11705471Abstract: A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.Type: GrantFiled: October 23, 2020Date of Patent: July 18, 2023Assignee: RAYTHEON COMPANYInventors: Sean P. Kilcoyne, George Grama, Scott S. Miller
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Patent number: 11694990Abstract: A display device includes a display panel including a display area and a non-display area defined therein and including a plurality of signal pads overlapping the non-display area, an electronic component including a base layer with an upper surface and a lower surface, a plurality of driving pads disposed on the lower surface of the base layer, and a plurality of driving bumps respectively disposed on the plurality of driving pads, the plurality of driving bumps being respectively connected to the signal pads, and a filler disposed between the display panel and the electronic component. A first hole is defined in the upper surface of the base layer, and the first hole does not overlap the plurality of driving bumps in a plan view.Type: GrantFiled: June 28, 2022Date of Patent: July 4, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Chan-Jae Park, Kikyung Youk, Sangduk Lee, Hyun a Lee, Daehwan Jang
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Patent number: 11688716Abstract: Provided is a semiconductor chip mounting tape. The semiconductor chip mounting tape comprises a tape base film including first and second surfaces opposite to each other; and an adhesive film including a third surface facing the first surface of the tape base film, and a fourth surface opposite to the third surface, wherein the adhesive film includes a plurality of voids therein, and the fourth surface of the adhesive film may be adhered to a semiconductor chip.Type: GrantFiled: February 5, 2021Date of Patent: June 27, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Soo Hwan Lee
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Patent number: 11682663Abstract: A display system includes (a) a display element having an organic light emitting diode-containing display active area disposed over a silicon backplane, (b) a display driver integrated circuit (DDIC) attached to the display element and electrically connected with the display active area, and (c) a thermal barrier disposed within the silicon backplane, where the thermal barrier is configured to inhibit heat flow through the silicon backplane and into the display active area.Type: GrantFiled: November 16, 2020Date of Patent: June 20, 2023Assignee: Meta Platforms Technologies, LLCInventors: Young Bae Kim, Donghee Nam, Min Hyuk Choi, Zhiming Zhuang
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Patent number: 11682652Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.Type: GrantFiled: March 10, 2021Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chan Li, Cheng-Hsien Chou, Sheng-Chau Chen, Cheng-Yuan Tsai