Patents Examined by Telly D Green
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Patent number: 11676942Abstract: A semiconductor structure includes a first die, a dielectric layer, a second interconnection structure, a second conductive pad and a conductive feature. The first die includes a first interconnection structure over a first substrate and a first conductive pad disposed on and electrically connected to the first interconnection structure. The first conductive pad has a probe mark on a surface thereof. The dielectric layer laterally warps around the first die. The second interconnection structure is disposed on the first die and the dielectric layer, the second interconnection structure includes a conductive via landing on the first conductive pad of the first die, and the conductive via is spaced apart from the first probe mark. The second conductive pad is disposed on and electrically connected to the second interconnection structure. The conductive feature is disposed on the second conductive pad.Type: GrantFiled: March 12, 2021Date of Patent: June 13, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh
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Patent number: 11676977Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.Type: GrantFiled: April 4, 2022Date of Patent: June 13, 2023Assignee: SONY GROUP CORPORATIONInventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada
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Patent number: 11670678Abstract: An integrated circuit (IC) structure includes a first cell and a second cell abutting the first cell. The first cell includes a first fin-like field-effect transistor (FinFET). The first FinFET includes a first channel region in a first fin extending along a first direction, and a first gate electrode extending across the first channel region in the first fin along a second direction different from the first direction. The second FinFET includes a second channel region in a second fin aligned with the first fin along the first direction, and a second gate electrode extending across the second channel region in the second fin along the second direction. The second fin has a smaller width than the first fin.Type: GrantFiled: August 10, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Jhon-Jhy Liaw
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Patent number: 11662066Abstract: An optoelectronic device including light-emitting components, each light-emitting component being adapted to emit a first radiation at a first wavelength, and photoluminescent blocks, each photoluminescent block facing at least one light-emitting component and comprising a single quantum well or multiple quantum wells, photoluminescent blocks being divided into first photoluminescent blocks adapted to convert by optical pumping the first radiation into a second radiation at a second wavelength, second photoluminescent blocks adapted to convert by optical pumping the first radiation into a third radiation at a third wavelength and third photoluminescent blocks adapted to convert by optical pumping the first radiation into a fourth radiation at a fourth wavelength.Type: GrantFiled: December 28, 2017Date of Patent: May 30, 2023Assignee: AlediaInventors: Wei Sin Tan, Philippe Gilet
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Patent number: 11664359Abstract: A display apparatus includes a display panel including a first surface and a second surface, where a display area which displays images is arranged in the first surface; a driving panel arranged on the display panel and including a first surface and a second surface; and a filling portion filled between the display panel and the driving panel. The display panel and the driving panel are stacked in a vertical direction in a cross-sectional view, and signal lines of the display panel may be electrically connected to signal lines of the driving panel, respectively, through a contact hole penetrating the display area and the driving panel.Type: GrantFiled: March 2, 2021Date of Patent: May 30, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Yijoon Ahn, Eoksu Kim
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Patent number: 11664406Abstract: A light-emitting device includes an inner light-emitting element having an n-sided polygonal shape (n is an integer of 3 or more) in a plan view with a peak emission wavelength in a range of 490 nm to 570 nm; m (m is an integer of 3 or more) outer light-emitting elements with a peak emission wavelength of 430 nm or greater and less than 490 nm; and a first phosphor with a peak emission wavelength in a range of 580 nm to 680 nm covering the inner light-emitting element and the m outer light-emitting elements. Each of n lateral surfaces of the inner light-emitting element faces a corresponding one of the m outer light-emitting elements in a top view.Type: GrantFiled: April 21, 2021Date of Patent: May 30, 2023Assignee: NICHIA CORPORATIONInventors: Takuya Miki, Naoki Matsuda
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Patent number: 11659743Abstract: A display panel includes a substrate having a non-display area surrounding an opening area, and a display area outside the non-display area, a plurality of display elements arranged in the display area, a plurality of first lines extending in a first direction and bypassing the opening area along an edge of the opening area, a plurality of second lines extending in a second direction that crosses the first direction and, the plurality of second lines bypassing the opening area along the edge of the opening area, and a plurality of third lines extending in the second direction and bypassing the opening area along the edge of the opening area, at least one of the plurality of third lines including a circuitous portion between neighboring first lines of the plurality of first lines in the non-display area.Type: GrantFiled: April 16, 2021Date of Patent: May 23, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Wonse Lee, Jintae Jeong, Jihyun Ka, Hwayoung Song
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Patent number: 11658169Abstract: A semiconductor device has a first substrate including an element region, a peripheral region that surrounds the element region, a first insulator with a first recess portion in the peripheral region, a first metal layer in the element region, and a first conductor in the peripheral region to surround the element region. A second substrate has an element region, a peripheral region that surrounds the element region, a second insulator with a second recess portion that faces the first recess portion, a second metal layer in contact with the first metal layer, and a second conductor that surrounds the element region of the second substrate.Type: GrantFiled: August 28, 2020Date of Patent: May 23, 2023Assignee: Kioxia CorporationInventor: Junichi Shibata
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Patent number: 11659732Abstract: A display device may include a display configured to emit light for displaying an image, a microlens array on the display and configured to collimate the image incident from the display so as to be delivered to the eyes of a user, the microlens array including a refractive index conversion layer in which a refractive index varies from region to region, and an optical path adjustment layer configured to collect light, emitted from the display and transmitted by the microlens array, and to space the display and the microlens array a preset distance apart from each other. Here, the refractive index conversion layer may include a polymer and liquid crystal molecules that interact with the polymer.Type: GrantFiled: June 24, 2021Date of Patent: May 23, 2023Assignee: Samsung Display Co., Ltd.Inventors: Su Jung Huh, Soo Min Baek, Ji Won Lee, Ju Hwa Ha
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Patent number: 11659713Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.Type: GrantFiled: October 6, 2021Date of Patent: May 23, 2023Inventors: Joo Won Park, Kyeong Jin Park, Kwang Soo Kim
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Patent number: 11653507Abstract: The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.Type: GrantFiled: February 24, 2022Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Marcus Johannes Henricus Van Dal, Timothy Vasen, Gerben Doornbos
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Patent number: 11652136Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a molding layer and a first capacitor. The first capacitor includes a first vertical conductive structure within the molding layer, a second vertical conductive structure within the molding layer, and a first high-k dielectric material between the first vertical conductive structure and the second vertical conductive structure.Type: GrantFiled: December 28, 2020Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Huan-Neng Chen, Wen-Shiang Liao
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Patent number: 11652113Abstract: An image sensor including a semiconductor substrate having a first surface and a second surface; and a pixel isolation film extending from the first surface of the semiconductor substrate into the semiconductor substrate and defining active pixels in the semiconductor substrate, wherein the pixel isolation film includes a buried conductive layer including polysilicon containing a fining element at a first concentration; and an insulating liner between the buried conductive layer and the semiconductor substrate, and wherein the fining element includes oxygen, carbon, or fluorine.Type: GrantFiled: November 5, 2021Date of Patent: May 16, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kook-tae Kim, Jin-gyun Kim, Soo-jin Hong
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Patent number: 11653511Abstract: Disclosed herein is an organic EL light-emitting apparatus including a plurality of pixels including a first pixel and a second pixel. The first pixel and second pixel share a common layer. The pixel other than the second pixel includes a non-common layer. The common layer contains a delayed fluorescent compound. The second pixel is configured to emit a light from the common layer. The pixel other than the second pixel is configured to emit a light from the non-common layer.Type: GrantFiled: February 5, 2016Date of Patent: May 16, 2023Assignee: IDEMITSU KOSAN CO., LTD.Inventor: Yuichiro Kawamura
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Patent number: 11646281Abstract: A semiconductor structure includes a first substrate including a first pad thereover, a second substrate including a bump thereover and a dielectric material. The first pad includes an inner portion and an outer portion being higher than and surrounding the inner portion. The bump is bonded to the inner portion and surrounded by the outer portion. The dielectric material is disposed between the first substrate and the second substrate to encapsulate the first pad and the bump.Type: GrantFiled: April 13, 2020Date of Patent: May 9, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hung-Jui Kuo, Hui-Jung Tsai, Tsao-Lun Chang
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Patent number: 11640988Abstract: Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure.Type: GrantFiled: July 30, 2021Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Szuya S. Liao, Michael L. Hattendorf, Tahir Ghani
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Patent number: 11637050Abstract: The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 ?m and 130 ?m, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.Type: GrantFiled: March 31, 2021Date of Patent: April 25, 2023Assignee: Qorvo US, Inc.Inventors: Anthony Chiu, Robert Charles Dry, Mihir Roy
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Patent number: 11631690Abstract: A three-dimensional memory device includes a first three-dimensional memory plane including first alternating stacks of first insulating layers and first word lines, and first bit lines electrically connected first vertical semiconductor channels, and a second three-dimensional memory plane including second alternating stacks of second insulating layers and second word lines and second bit lines electrically connected to second vertical channels. An inter-array backside trench laterally extend between the first three-dimensional memory plane and the second three-dimensional memory plane, and filled with an inter-array backside insulating material portion that provides electrical isolation between the three-dimensional memory planes.Type: GrantFiled: December 15, 2020Date of Patent: April 18, 2023Assignee: SANDISK TECHNOLOGIES LLCInventor: Teruo Okina
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Patent number: 11626418Abstract: A three-dimensional memory device includes an alternating stacks of insulating layers and electrically conductive layers. Memory opening fill structures located in memory openings include a memory film and plural vertical semiconductor channels.Type: GrantFiled: December 11, 2020Date of Patent: April 11, 2023Assignee: SANDISK TECHNOLOGIES LLCInventor: Takeki Ninomiya
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Patent number: 11609391Abstract: A semiconductor package includes a semiconductor die, a device layer, an insulator layer, a buffer layer, and connective terminals. The device layer is stacked over the semiconductor die. The device layer includes an edge coupler located at an edge of the semiconductor package and a waveguide connected to the edge coupler. The insulator layer is stacked over the device layer and includes a first dielectric material. The buffer layer is stacked over the insulator layer. The buffer layer includes a second dielectric material. The connective terminals are disposed on the buffer layer and reach the insulator layer through contact openings of the buffer layer.Type: GrantFiled: May 19, 2020Date of Patent: March 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen