Abstract: A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.

Abstract: A three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. An example semiconductor device generally includes an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads, and a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads and is bonded to the first oxide material b. The semiconductor device may also include a substrate disposed above the second plurality of pads, one or more passive devices adjacent to the substrate, and one or more vias formed through the substrate, wherein at least one of the second plurality of pads is coupled to the one or more vias.

Abstract: A via for semiconductor devices is disclosed. Implementations of vias for semiconductor devices may include: a semiconductor substrate that includes a first side; a via extending from the first side of the semiconductor substrate to a pad; a polymer layer coupled along an entire sidewall of the via, the polymer layer in direct contact with the pad; and a metal layer directly coupled over the polymer layer and directly coupled with the pad.

Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, a first chip pad on a bottom surface of the semiconductor chip and adjacent to a first lateral surface in a first direction of the semiconductor chip, the first lateral surface separated from the first chip pad from a plan view in a first direction, and a first lead frame coupled to the first chip pad. The first lead frame includes a first segment on a bottom surface of the first chip pad and extending from the first chip pad in a second direction opposite to the first direction and away from the first lateral surface of the semiconductor chip, and a second segment which connects to a first end of the first segment and then extends along the first direction to extend beyond the first lateral surface of the semiconductor chip after passing one side of the first chip pad, when viewed in the plan view.

Abstract: An organic light emitting display device includes a substrate, a pixel structure, and a touch sensor electrode. The substrate includes a sub-pixel region and a transparent region. The pixel structure is disposed in the sub-pixel region on the substrate. The touch sensor electrode is disposed in the transparent region on the substrate.

Abstract: A semiconductor device including an insulating circuit board. The insulating circuit board has an insulating plate, a plurality of circuit patterns disposed on a front surface of the insulating plate, any adjacent two of the circuit patterns having a gap therebetween, each circuit pattern having at least one corner, each corner being in a corner area that covers the corner and a portion of each gap adjacent to the corner, and a buffer material containing resin, applied at a plurality of corner areas, to fill the gaps in the plurality of corner areas.

Abstract: A semiconductor device includes, a semiconductor element, a wiring member arranged to sandwich the semiconductor element, a sealing resin body. The semiconductor element has an SBD formed thereon with a base material of SiC which is a wide band gap semiconductor. The semiconductor element has two main electrodes on both surfaces. The wiring member includes (i) a heat sink electrically connected to a first main electrode and (ii) a heat sink and a terminal electrically connected to a second main electrode. The semiconductor device further includes an insulator. The insulator has a non-conducting element made of silicon. The insulator has joints on both of two surfaces for mechanical connection of the heat sinks.

Abstract: Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.

Abstract: A light-emitting device, including a circuit substrate, a first light-emitting diode, and a first fixing structure, is provided. The circuit substrate includes a substrate, a first pad, a flat layer, and a first electrical connection material. The first pad and the flat layer are located on the substrate. The flat layer has a first opening overlapping the first pad. The first electrical connection material is located in the first opening and is electrically connected to the first pad. The first light-emitting diode is located on the flat layer and in contact with the first electrical connection material. The first fixing structure is located between the first light-emitting diode and the flat layer. The vertical projection of the first fixing structure on the substrate is located in the vertical projection of the first light-emitting diode on the substrate.

Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

Abstract: Provided is a cadmium zinc telluride (CdZnTe) single crystal including a main surface that has a high mobility lifetime product (?? product) in a wide range, wherein the main surface has an area of 100 mm2 or more and has 50% or more of regions where the ?? product is 1.0×10?3 cm2/V or more based on the entire main surface, and a method for effectively producing the same.

Abstract: A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a first substrate, a first interlayer dielectric (ILD) layer on the first MOS transistor, a second substrate on the first ILD layer, and a second MOS transistor on a second substrate. Preferably, the semiconductor device includes a static random access memory (SRAM) and the SRAM includes a first pull-up device, a second pull-up device, a first pull-down device, a second pull-down device, a first pass-gate device, a second pass-gate device, a read port pull-down device, and a read port pass-gate device, in which the read port pull-down device includes the first MOS transistor and the read port pass-gate device includes the second MOS transistor.

Abstract: A method of using an optoelectronic semiconductor stamp to manufacture an optoelectronic semiconductor device comprises the following steps: a preparation step: preparing at least one optoelectronic semiconductor stamp group and a target substrate, wherein each optoelectronic semiconductor stamp group comprises at least one optoelectronic semiconductor stamp, each optoelectronic semiconductor stamp comprises a plurality of optoelectronic semiconductor components disposed on a heat conductive substrate, each optoelectronic semiconductor component has at least one electrode, and the target substrate has a plurality of conductive portions; an align-press step: aligning and attaching at least one optoelectronic semiconductor stamp to the target substrate, so that the electrodes are pressed on the corresponding conductive portions; and a bonding step: electrically connecting the electrodes to the corresponding conductive portions.

Abstract: A semiconductor structure includes a metal gate structure disposed over a semiconductor substrate, an interlayer dielectric (ILD) layer disposed over the metal gate structure, and a gate contact disposed in the ILD layer and over the metal gate structure, where a bottom surface of the gate contact is defined by a barrier layer disposed over the metal gate structure, where sidewall surfaces of the gate contact are defined by and directly in contact with the ILD layer, and where the barrier layer is free of nitrogen.

Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.

Abstract: A semiconductor package includes: an insulating substrate having opposing first and second main sides; a power semiconductor die embedded in, and thinner than or a same thickness as, the substrate, and including a first load terminal bond pad at a first side which faces a same direction as the substrate first main side, a second load terminal bond pad at a second side which faces a same direction as the substrate second main side, and a control terminal bond pad; electrically conductive first vias extending through the substrate in a periphery region; a first metallization connecting the first load terminal bond pad to the first vias at the substrate first main side; solderable first contact pads at the substrate second main side and formed by the first vias; and a solderable second contact pad at the substrate second main side and formed by the second load terminal die bond pad.

Abstract: An interconnect structure includes a plurality of first pads, a plurality of second pads, a plurality of first conductive lines in a first layer, a plurality of second conductive lines in a second layer, and a plurality of nth conductive lines in an nth layer. The first pads and the second pads respectively are grouped into a first, a second and an nth group. Each of the first pads in first group is connected to one of the second pads in the first group by one of the first conductive lines. Each of the first pads in the second group is connected to one of the second pads in the second group by one of the second conductive lines. Each of the first pads in the nth group is connected to one of the second pads in the nth group by one of the nth conductive lines.