Abstract: A memory that supports non-aligned memory accesses includes a field address generator circuit, multiple field memories, and a data rotation circuit. The field address generator circuit generates multiple field addresses in response to an address associated with a memory access. Each field memory receives one of the field addresses from the field address generator circuit. The data rotation circuit rotates data associated with the memory access based upon the memory access address to support a non-aligned access. The memory can support either non-aligned read accesses or non-aligned write accesses. A method for performing non-aligned read or write memory accesses is also described.

Abstract: A page table entry management method and apparatus provide the Microkernel System with the capability to program the memory management unit on the PowerPC family of processors. The PowerPC processors define a limited set of page table entries (PTEs) to maintain virtual to physical mappings. The page table entry management method and apparatus solves the problem of a limited number of PTEs by segment aliasing when two or more user processes share a segment of memory. The segments are aliased rather than duplicating the PTES. This significantly reduces the number of PTEs. In addition, the method provides for caching existing PTEs when the system actually runs out of PTEs. A cache of recently discarded PTEs provides a fast fault resolution when a recently used page is accessed again.

Abstract: Read access to a memory device is controlled by comparing an input control code with a predetermined code stored in the memory device. The comparison is performed inside the memory device, and read access is enabled or disabled according to the result. The control code can be used to select one of several memory devices connected to a common bus, or to provide security for information stored in the memory device.

Abstract: An address queue in a processor having the capability to track memory-dependencies of memory-access instructions is disclosed. The queue includes a first matrix of RAM cells that tracks a first dependency relationship between a plurality of instructions based upon matching virtual addresses (that identify a common cache set) and the order of instructions in the queue. To facilitate out-of-order instruction execution, dependencies may be tracked before virtual addresses are actually calculated based upon a presumption of dependency. Such dependency is dynamically corrected as addresses become available. The same comparison mechanism used to determine matching virtual addresses for the dependency relationship may also be used to read status bits of a cache set being accessed.

Abstract: A system and method are provided for remotely managing memory in a programmable portable information device, such as a programmable watch, from an external computer. The portable information device has an optical sensor and a rewritable data memory. The computer has a frame-scanning graphics display device and a memory with a capacity larger than that of the device memory. The device memory is mapped into a portion of the computer memory to create a virtual device memory therein. An input device for the computer is provided to permit a user to enter programming changes to be made to the information device,. The programming changes alter the virtual device memory within the computer memory from an initial arrangement to a modified arrangement. Upon modification, a memory manager resident in the computer determines what memory transactions are effective to change the virtual device memory from its initial arrangement to its modified arrangement.

Abstract: A storage unit comprises a plurality of storage modules, each of which is dynamically assigned to and used as each area in a main storage (MS) or an extended storage (ES). The storage unit or a system controller has address arrays for MS and for ES which store information indicating which of the storage modules comprised in the storage unit each area in the MS and the ES corresponds to. When the contents of the MS/ES address arrays are rewritten to change a storage module belonging to the ES to a storage module belonging to the MS, a page-in operation is realized without executing an actual data move operation. Similarly, a page-out operation is realized without executing an actual data move operation by changing a storage module belonging to the MS to a storage module belonging to the ES.

Abstract: In a method and apparatus for addressing memory there is a procedure for providing a word with fixed width, having a fixed number of bits to be used for addressing variable width data, and having a width defining field and address field, is disclosed. In addition, a procedure for addressing memory with a fixed width word, having a fixed number of bits, to be used for addressing data and having a substitution field and an address field, is discussed.

Abstract: A microprocessor including address generation units configured to perform address generation for memory operations is provided. A reservation station associated with one of the address generation units receives the displacement from an instruction and an indication of the selected segment register upon decode of the instruction in a corresponding decode unit within the microprocessor. The displacement and segment base address from the selected segment register are added in the reservation station while the register operands for the instruction are requested. If the register operands are provided upon request (as opposed to a reorder buffer tag), the displacement/base sum and register operands are passed to the address generation unit. The address generation unit adds the displacement/base sum to the register operands, thereby forming the linear address. If register operands are not provided upon request (i.e.

Abstract: A device for replacing defective storage locations with working storage locations comprises receiving means for receiving an incoming address for accessing a storage location, comparing means for comparing the incoming address with all of the addresses of known defective storage locations, and directing means for directing accesses to an alternative location when the incoming address matches one of the addresses of known defective storage locations. There is one alternative storage location and one comparing means for each known defective storage location. In this invention only a portion of the incoming address is used in the comparing means. In addition, each of the comparing means may use a different portion of the address for accessing a storage location.

Abstract: A structure for, and a method of operating, a descriptor cache to store segment descriptors retrieved from memory. In one embodiment, the descriptor cache is direct-mapped and addressed by a first part of the physical address in memory at which a desired descriptor is stored. If the desired descriptor is not stored in the addressed entry of the descriptor cache then the descriptor is retrieved from a descriptor table held in memory and loaded into the addressed entry of the descriptor cache (which will then be able to satisfy future requests for the same descriptor). At the same time, a second part of the descriptor's physical address is loaded into an entry of a physical address cache corresponding to the addressed entry of the descriptor cache.

Abstract: Aspects of the present invention are directed to communications circuits and method that utilize associative memories for providing telephony switching of data between different time slots in one or more time division multiplexed (TDM) serial data lines or streams. The communications circuit may include a first content-addressable memory block and a second content-addressable memory block each of which receive the same address for independently generating tags for accessing a data memory to provide data to or receive data from TDM data lines.

Abstract: A memory management and control system that is selectable at the application level by an application programmer is provided. The memory management and control system is based on the use of policy modules. Policy modules are used to specify and control different aspects of memory operations in NUMA computer systems, including how memory is managed for processes running in NUMA computer systems. Preferably, each policy module comprises a plurality of methods that are used to control a variety of memory operations. Such memory operations typically include initial memory placement, memory page size, a migration policy, a replication policy and a paging policy. One method typically contained in policy modules is an initial placement policy. Placement policies may be based on two abstractions of physical memory nodes. These two abstractions are referred to herein as "Memory Locality Domains" (MLDs) and "Memory Locality Domain Sets" (MLDSETs).

Abstract: A computer executable program method for automating the upgrade of a storage medium, such as a disk drive, in a computer system is disclosed. The computer based method is preferably implemented with a series of computer-executable instructions stored on a computer-readable medium, such as a magnetic disk or CD-ROM. When executed on a computer, the program method automatically performs the series of operations needed to configure, partition and format the upgrade disk drive. The method also provides the option of adjusting system parameters so as to account for any changes to logical device designations resulting from the installation of the upgrade disk drive. Once installed, the program method optionally provides the user with the option of utilizing the upgrade disk drive as the new system boot device, or as a secondary/slave device.

Abstract: A method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes selected for translating a number of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each virtual address received by the selection unit, the selection unit positions a field in that virtual address based on the page size selected for translating that virtual address. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator identifies an entry in a page table based on those bits.

Abstract: A microcontroller with a page zero mode where a memory address space is restricted to one page of a multiple page address space to produce improved performance. Address mapping logic and memory segment selection logic limits addresses to the least significant 16 bits of a possible 24 bit address. Different or alternate microcode program controlled instruction sequences with eliminated high order address clock cycles are used in the page zero mode.

Abstract: A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plurality of match lines, and a second logic gate has an input coupled to a second match line of the plurality of match lines. A first switch is coupled between an output of the first logic gate and a first word line, and a second switch is coupled between an output of the second logic gate and a second word line. The first switch is controlled by the output of the second logic gate such that the first switch is opened when the second match line has a second logic value and closed when the second match line has a first logic value. The second switch is controlled by the output of the first logic gate such that the second switch is opened when the first match line has the second logic value and closed when the first match line has the first logic value.

Abstract: A storage device has a relative address table. An address is sequentially generated by an address adder based on a start address and a plurality of relative addresses held in the relative address table. When a pattern of the address is unchanged, a succeeding access is processed without resetting the relative addresses in the relative address table.

Abstract: An improved method for loading a cache is described. The present invention monitors memory access to identify specific types of memory access, for example, requests to launch executable program code stored in a hard disk drive. The method maps the stored program code into a plurality of memory blocks. The memory block access during the launching of the executable program code is then profiled. When the computer remains idle for a predetermined time the profiling process is stopped. Alternatively, if the computer does not remain idle, for the predetermined time, the profiling process is stopped after a timeout period. The profile is then evaluated to identify the most frequently accessed memory blocks. A list of the most frequently accessed memory blocks is stored. The number of memory blocks stored in the list depends upon the size of the cache. The file access system is monitored to identify the next time that a profiled memory access process is initiated.

Abstract: A methodology that provides detection of cache coherency errors in addition to detection of inefficient cache use by a cache master is disclosed. A model of the cache with storage for the address and data contained in each cache line and a flag indicating the state of the cache line (e.g., MESI state, or other cache coherency protocol state) is utilized. In addition, the cache model object also holds a dynamically allocated list (the cycle list) of bus cycles. This list is used to store pointers to non-cache bus cycles initiated in the multi-bus system. Cache bus cycles can update the state of the cache model object and can also instruct the cache model to perform coherency tests on pending non-cache bus cycles in the cycle list. When all protocol tests for a non-cache bus cycle have been successfully completed, no further coherency tests are performed on that bus cycle.

Abstract: An interleaving process in which data is interleaved or interleaved data is de-interleaved. Input data units are distributed over a plurality of output groups of data units. In GSM telephony, input bits are distributed over nineteen transmission bursts. Incoming data units are written to a contiguous RAM and output groups are read from said RAM. Addressing circuitry controls the writing and reading to the RAM, such that data units are stored until required for an output group. After data has been read, these read locations are re-used for the storage of new input data, such that the duration over which a particular memory location stores a data unit depends upon the interleaving process delay for that particular data unit. The addressing circuitry includes modulo counters, each arranged to generate addressing signals for a respective set of memory locations within the RAM. Look-up tables are used to select modulo counts so as to provide conventional addresses to the RAM.