Abstract: Read Only Memory (ROM) (10) data may be selectively inverted to decrease energy dissipation. Within the ROM (10), a plurality of memory cells (16) are connected to bit-line (18) and word-line (20) and store data, which determines the loading for a particular line. Line loading may be manipulated by accessing initial mapping information (23) of the ROM (10) and calculating the line loading on each line (18 or 20) and whenever a line's load exceeds a threshold, data stored in the memory cells (16) on the particular line (18 or 20) are inverted. Having done this, new mapping information (23) is produced and used to retrieve data from the ROM (10).

Abstract: A method of and apparatus for rapidly modifying the user base registers of an instruction processor. In accordance with the present invention, a load base register user instruction may request an operand from a cache memory, wherein the requested operand may provide a new L field and a new bank descriptor index field. An unconditional compare may be made between the new L,BDI fields and the prior L,BDI fields, regardless of whether the requested operand providing the new L,BDI fields actually resides in a corresponding operand cache. In parallel therewith, the operand cache may determine whether or not the requested operand that provided the new L,BDI fields actually resides in the cache memory. A selector block may then determine if the new L,BDI fields match the previous L,BDI fields, and if the requested operand that provided the new L,BDI fields actually resides in the cache memory. If so, a fast load base register algorithm may be used to load the base register.

Abstract: A first and a second input ports, the sum of whose inputs is greater than an integer n, receive pairs of first words of k bits and of second words of n-k bits, each set of n bits representing an address item (ADI) for a point (PO) of a two-dimensional space of points (IM) associated with data coded on 2.sup.d bits, the respective bits of the first and second words representing two coordinates (X, Y) of the point in the said space. A configuration input receives a value of k (k1, k2, k3), chosen to be positive or zero and less than or equal to n, and representative of a geometrical configuration chosen for the two-dimensional?s!?pace! space (IM).

Abstract: A processor having an address generation unit (AGU) for generating an address corresponding to an entry that is to be fetched. The AGU includes a segment register file for storing address segments, and a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order. The AGU further includes a circuit for executing a single microinstruction to perform read and write operations on a selected field of the second address segments stored in the segment register file.

Abstract: A method and apparatus for providing access to a banked peripheral memory via a contiguous linear address space. The present invention provides a linear address space having a present region that is mapped to a host memory region of a computer system. The present invention further provides a relocatable selector that provides access to a portion of the linear address space. Accessing programs exchange data with the banked peripheral memory via the relocatable linear address space. When an accessing program references an address of the relocatable address base that is not mapped to the present region, the relocatable linear address space is positioned so that the referenced address maps to the present region. Additionally, a bank of the peripheral memory that corresponds to the referenced address is also mapped into the host memory region so as to enable the accessing program to exchange data with the banked peripheral memory via the relocatable linear address space.

Abstract: A multiple-word virtual address flexibly expands the virtual address space of a computer system without requiring the modification of the word size of the computer system. In a memory system having a virtual memory mapped to an absolute memory, the virtual memory is divided up into multiple levels each having a plurality of memory banks. Each memory bank has a plurality of words. The multiple-word virtual address provides a plurality of words for specifying the virtual memory level, memory bank, and offset word within the memory bank, to describe a selected memory location. Special instructions are added to the instruction set architecture to set up a window of program visibility, called a peephole, into a selected area of the expanded virtual memory. Existing programs are compatible with the multiple-word addressing scheme, and can also reference virtual memory through a defined peephole. New programs using multiple-word virtual addresses can still call procedures requiring single word virtual addresses.

Abstract: An operating system component allocates locked stack memory pages to threads on an as needed basis. Each thread has a permanent locked stack. A second locked stack page is mapped to each thread. If a thread is using the assignable locked stack page when the system scheduler switches away from that thread, the assignable stack page becomes owned by that thread. When the system scheduler switches to a thread the assignable stack page mapped to that thread is checked to see if it is owned by another thread. If so, an unowned assignable stack page is mapped to the thread prior to switching to that thread. The size of the pool of locked assignable stack pages is adjusted dynamically. If the number of unowned assignable stack pages exceeds a threshold, locked stack pages are released. If the number of locked assignable stack pages falls below a predetermined number, additional assignable stack pages are allocated.

Abstract: A portable electronic smart card for use as a medium for the dissemination among consumers of digitized data such as texts, pictures or game programs. The smart card is connected to user systems through a reduced set of contacts including, regardless of capacity, 3 contacts for transmitting address signals (CA1, CA2, INC/DEC), 8 contacts for transmitting data signals (D0-D7), and 5 different leading and control signals (VCC, VPP, GND, PGM, OE). For memory addressing, the card contains two up-down counter (11 and 12) which receive pulses from lines CA1, CA2 and INC/DEC.

Abstract: An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The column address is changes in response to a rising edge of a column address signal (CAS*). The memory also includes a buffer circuit which latches the output of the address counter in response to the falling edge of the column address signal. Memory cells are accessed in a burst manner on the falling edge of the column address signal using the address latched in the buffer.

Abstract: A method is provided for recovering the effective address of memory instructions in an out-of-order microprocessor for use by an exception handler upon the occurrence of one of an exception and a systems management interrupt. The microprocessor comprises at least one execution unit for executing a plurality of instructions out-of-order and a re-order buffer having storage locations for buffering result data produced from the execution of the plurality of instructions. Each instruction is associated with a location designator to identify a unique storage location within the re-order buffer in which the result data for an executed instruction is written. The microprocessor further comprises a memory order buffer having storage locations for buffering memory instructions waiting for access to memory for execution, these storage locations also being identified by corresponding location designators.

Abstract: A method and system for memory management and address translation mapping of pools of logical partitions for BAT and TLB entries in a data processing system is provided. An entry in an address translation buffer is created that is associated with a particular block of virtual memory comprised of a plurality of logical partitions that are grouped in one or more pools of logical partitions, wherein the size of each pool of logical partitions is equal to a preselected page size for real memory, and wherein the entry maps each pool of logical partitions to a page of real memory within a sector of real memory, wherein the size of the sector is a function of the size of the associated block of virtual memory.

Abstract: In a first step of an optical disk write method, an area for logical format information is reserved on an optical disk; in a second step, variable-length packets, each packet comprising a demarcation block and a variable-length data block including a new file or a corrected file, on a data area, in response to a write instruction for writing the new file or the corrected file; in a third step, a volume history indicating a logical structure of files is maintained and file logical information for written and deleted files is chronologically appended to the volume history; in a fourth step, logical format information of the optical disk is produced based on the volume history, in response to an instruction for finalization; and in a fifth step, the logical format information, a lead-in area and a lead-out area are provided on the optical disk.

Abstract: A method and system for efficient memory management in a data processing system which utilizes a memory management unit to translate effective addresses into real addresses within a translation lookaside buffer is disclosed. During a first mode of operation a selected number of effective address identifiers are stored in the translation lookaside buffer. In association with each virtual address identifier is a corresponding real address entry for a single memory block wherein selected virtual addresses may be translated into corresponding real addresses utilizing the translation lookaside buffer.

Abstract: A method and system for address translation mapping of logical partitions for address translation buffer entries in a data processing system is provided. The method comprises receiving a logical address for a memory reference to a selected logical partition of a plurality of logical partitions of a particular block of virtual memory, wherein the block of virtual memory is divided into the plurality of logical partitions, and wherein the logical address includes a plurality of logical partition selection bits selecting the selected logical partition from among the plurality of logical partitions.

Abstract: A method and apparatus for implementing virtual memory having multiple selected page sizes are provided. A virtual address includes a map index and a frame offset. A selector mechanism receives the virtual address frame offset and generates an offset and index. A frame map table indexes the virtual address map index and the selector generated index and generates a base address. The frame map table generated base address and the selector generated offset are combined to provide a physical address.

Abstract: A method and apparatus for configuring the address space of a computer is described. According to the present invention, a computer system has a full address space and includes at least one base unit, at least one expansion unit and a microprocessor core. The microprocessor core issues access addresses. The full address space includes a base address space and an expanded address space. The base address space is addressed by an M bit address and the expanded address space is addressed by an N bit address (N.gtoreq.M). Each base unit is mapped to an address within the base address space, and the base unit address is mirrored in the expanded address space. Each expansion unit is mapped to an address within the expanded address space. An address configuration circuit in the computer system includes an address space remapping circuit for selectively remapping or not remapping base units out of the base address space.

Abstract: A method and an apparatus for profile guided TLB's (translation look-aside buffer) and cache optimization in an operating system. A typical operating system has a working set of information for any application which is running at some time. This working set of information can be written out by the operating system in some section of the object file. Once this information is in the object file, it may be utilized by the operating system in various ways. The method and apparatus decreases TLB misses for the benchmarks, disables infrequently used pages from disturbing the caches, and provides better rates on caches. This and many other advantages of the invention allow an increased efficiency and optimization of a given operating system.

Abstract: A computer memory system is disclosed with an input/output circuitry capable of separating the load separating the load capacitance of an output circuit of a semiconductor memory connected to a memory bus from the memory bus. In order to separate the load capacitance of a semiconductor memory connected to a memory bus signal line, a Schottky diode is arranged between the semiconductor memory and the memory bus line, and a voltage control circuit is provided to control whether a reverse bias voltage is applied to the Schottky diode. The speed of signal transmission does not decrease even when a large number of semiconductor memories are connected to the memory bus since the load capacitance of the semiconductor memories is separated from the bus. Therefore, it is possible to construct a high speed and large capacity memory system.

Abstract: A system and method for generating row addresses for a memory structure on a column by column basis. In accordance with the novel method, a column read start address (SC) is subtracted from a column address (COL) to provide a column offset. Next, the column offset is multiplied by the multiplicative inverse of the skip period in modulo (SPM.sup.-1) to provide a first product. The first product is multiplied by a skip period between data strings to provide a second product. The second product is divided by a number (NC) which represents the number of columns in the memory structure to provide a first quotient. Finally, a base row address of a first row to be read (BRA) is added to the first quotient to provide a row address (RA). In a specific embodiment, the step of multiplying the column offset by the multiplicative inverse of the skip period in modulo includes the step of converting the first product to a modulo product.

Abstract: Memory management unit with address translation function improves the translation speed for virtual addresses and minimizes the deviation in response time. The memory management unit translates partially and entirely the virtual address into an physical address by using four extended auxiliary caches. And the memory management unit performs table walks for the zest part of the virtual address which is not translated, by using four tables contained in main memory.