Abstract: An associative memory device having a high speed and good performance is provided without degrading the simple design of a peripheral circuit of a conventional associative memory. The associative memory device has an N-bit first buffer and an M-bit second buffer in which W-bit data is stored through a data input port, detection device for detecting that the W-bit data is input to the first buffer k times or to the second buffer r times, a switch for alternately switching buffers in which the W-bit data is stored, and a search control for performing a search operation for a memory region by using data in the first or second buffer. By using data in the first or second buffer, during the search operation for the memory region of the associative memory, the W-bit data for the next search operation is input to the second or first buffer.

Abstract: An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address translation unit of the present invention is utilized in a computer system. The computer system comprises a first bus; processors with embedded caches and memory coupled to the first bus; a second bus; a network logic coupled to the second bus, wherein the network logic includes an address translation unit; and a bus bridge coupled to the first bus and to the second bus.

Abstract: A virtual memory lock is placed upon a region of physical memory within a computer system in response to an I/O request through the use of a range lock. Each range lock represents pages of virtual memory that are present and locked in the physical memory. The range locks are cached in memory and used subsequently to process a lock or unlock request, thus avoiding constant locking or unlocking. Regions of memory that are locked, but have no outstanding I/O operations may still have a range lock existing corresponding to that region. If no range lock exists for an I/O request, the virtual memory lock function is called and a range lock is created for that region. If a range lock exists, its usage counter is incremented. Upon notification of the completion of an I/O operation upon a particular region, the usage counter for the range lock corresponding to that region is decremented, and the range lock continues to exist even if there are no outstanding I/O requests for that region.

Abstract: A new virtual memory system is disclosed having a virtual address space including a gap of inaccessible virtual addresses within the virtual address space. A new virtual memory allocation routine is disclosed providing a starting address of accessible virtual addresses allocated to a currently executing process in a response to a request. The accessible virtual addresses are virtually contiguous, and include no addresses from within the gap of inaccessible virtual addresses. A new virtual memory deallocation routine is further disclosed providing deallocation of ranges of virtual addresses which may or may not include addresses within the inaccessible gap.

Abstract: A method of recording digital signals on a disk which has at least a first recording surface and a second recording surface both being readable from a same side of the disk. The digital signals are in the form of a data frame which includes at least n data blocks (n is a natural number).

Abstract: A fetching apparatus (20) is for use in a data processing equipment comprising a processor (11) and a main memory (12). The main memory has a page structure comprising a plurality of pages each of which has a plurality of page data. The fetching apparatus is located between the processor and the main memory. The fetching apparatus fetches the page data of a specific one of the pages as fetched page data from the main memory and supplies the fetched page data to said processor. The fetching apparatus comprises a plurality of registers (23-1 to 23-K) each of which is for memorizing the fetched page data. A table section (24) is for memorizing addresses corresponding the page data in each of the page. The table section further memorizes, as data transfer locations, the memory areas corresponding to the addresses.

Abstract: The present invention relates to a computer system in which linear memory attributes are specified. Physical memory attributes may also be specified in physical attribute registers. A memory attribute palette (MAP) receives index signals and selects linear memory attributes in response to the index signals. An effective memory attribute selector receives selected linear memory attribute signals and, if present, the physical memory attribute signals and, in response thereto, selects effective memory attribute signals to present an effective memory attribute. In a preferred embodiment, the linear memory attributes may be programmably written into one or more registers, thereby allowing a program or OS flexibility in the choice of memory attributes, including memory attributes not currently used. The invention allows a program to apply a memory attribute of choice to a particular section of memory, thereby allowing the computer system to provide higher performance.

Abstract: A method of addressing a computer subsystem memory comprised of establishing an aperture having a predetermined page size, addressing the memory at address boundaries defining multiples of half the page size, and reading or writing a page of data from or to the subsystem memory using the established aperture at consecutive memory locations beginning at one of the boundaries.

Abstract: An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM (SDRAM) is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a SDRAM during a test process in real time and generates column addresses for the SDRAM by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, a Z address signal, and an operation mode control signal, a conversion memory that outputs data based on a conversion table, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with a burst length control signal.

Abstract: A memory speed testing circuit including a memory addressing circuit (11, 13, 15) for sequentially providing to the address input of the memory device a binary address A and a binary address A which is a binary 1's complement of the binary address A, wherein the binary address A is provided within a selected time interval after the provision of the binary address A when the memory device is in a read mode; a data circuit (21, 23, 24) for generating a first binary test word and a second binary test word that is a 1's complement of the first binary test word; wherein the first binary test word is input to the data port of the memory device when the binary address A is provided the address input of the memory device when the memory device is in the write mode, and wherein the second binary test word is input to the data port of the memory device when the binary address A is provided to the address input of the memory device when the memory device is in the write mode; and a comparator (25) for comparing the firs

Abstract: A data recording disk drive includes a system and method for mapping around skip sectors, both bad sectors and spare sectors. A received logical block address is converted to a corresponding physical block address by mapping through a set of tables. A first table includes entries for virtual tracks which group together LBAs having shared high order bits. A second table contains entries for the skip sectors. The high order bits of a given LBA are used to select an entry in the first table, which entry is an index into the second table. Starting from the index point, the second table is searched, using the low order bits of the LBA, for a skip sector beyond the LBA value. Once the appropriate skip sector is found, the index of this skip sector within the second table is added to the LBA to compute the PBA. The PBA is then mapped to a zone, cylinder, head, sector location on the disk drive.

Abstract: A method and apparatus for generating a modulo address for accessing a circular buffer. The method and apparatus accept as inputs a length L of the circular buffer, a current address A of the circular buffer, and an offset M between the current address and the next address to be generated. The offset M may be positive or negative. During operation of the present invention, the current address A first is broken down into a base address B and an offset from the base address a. Then, in accordance with the length L and the offset M, the invention determines an absolute offset and a wrapped offset. One of these offsets is added to the base address B to generate a next address for the circular buffer. The determination of which offset to add to the base address B is made by performing one of two comparisons.

Abstract: This invention overcomes the address size backward compatibility problem by first subtracting the segment base address from the linear destination address of a branch instruction to generate a virtual destination address. It is assumed that the branch instruction destination address is n bits long with m most significant bits. It is desired to provide backward compatibility in the n-bit processor for branch instruction code written for processors utilizing instruction address fields of size (n-m) bits. After obtaining the virtual address, if any of the m most significant bits are non-zero, then those m bits are set to zero to thereby generate a corrected virtual address. If such a compatibility correction is necessary, then a clear signal is asserted to flush all state of the processor that resulted from instructions being fetched after the branch instruction was fetched. The corrected virtual address is added back to the segment base address to generate a corrected linear address.

Abstract: A flash disk card using a flash memory is provided with MPU for converting the cylinder, head and sector numbers, which are input from a host device, into a logical block address (LBA) and a sector address in block format, determining a physical block address (PBA) having the same size as that of an erase block from the logical block address with reference to a logical/physical block address conversion table stored in the flash memory, and accessing the flash memory on the basis of the physical block address. The flash disk card permits a decrease in size of the address conversion table, can be constructed at low cost, and has no need for constructing the table at each time a power supply is turned on.

Abstract: A microprocessor or microcontroller architecture which utilizes a 64 byte-register file in a unique manner. The lowest 16 bytes of the register file can be accessed as 16 8-bit registers (R0-R15), the lowest 32 bytes can also be accessed as 16 32-bit (word) registers (WR0-WR30), and the entire register file can be accessed as 16 64-bit (double word or Dword) registers (DR0-DR60). In this manner, various combinations of 8/16/32-bit registers are provided without wasting the register file. While providing at least 16 8/16/32-bit registers, only four bits are necessary to encode a register, thereby allowing two byte register-to-register instructions. The register file and an instruction sequencer operate to provide the 64 byte-register file which can be accessed so that the lowest 16 bytes of the register file are accessed as 16 8-bit registers (R0-R15), the lowest 32 are accessed as 16 word registers (WR0-WR30), and the entire register file is accessed as 16 double word registers (DR0-DR60).

Abstract: A bridge logic takes non-burst write cycles that appear one at a time as an address followed by an associated data word on a first bus, detects consecutive addresses, and uses this information to create burst cycles on a second bus that has protocols that allow burst cycles such as a Peripheral Component Interconnect (PCI) bus.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.

Abstract: A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plurality of match lines, and a second logic gate has an input coupled to a second match line of the plurality of match lines. A first switch is coupled between an output of the first logic gate and a first word line, and a second switch is coupled between an output of the second logic gate and a second word line. The first switch is controlled by the output of the second logic gate such that the first switch is opened when the second match line has a second logic value and closed when the second match line has a first logic value. The second switch is controlled by the output of the first logic gate such that the second switch is opened when the first match line has the second logic value and closed when the first match line has the first logic value.

Abstract: Provides within a semiconductor chip a plurality of internal DRAM arrays connected to each section data bus. A cross-point switch simultaneously connects the plural section data buses to a corresponding plurality of port registers that transfer data between a plurality of ports (I/O pins) on the chip and the section data buses in parallel in either data direction to effectively support a high multi-port data rate to/from the memory chip. For any section, the data may be transferred entirely in parallel between the associated port and a corresponding port register, or the data may be multiplexed between each port and its port register in plural sets of parallel bits. Each of the DRAM banks in the chip is addressed and accessed in parallel with the other DRAM banks through a bank address control in the chip which receives all address requests from four processors in a computer system.

Abstract: Memory system for internally rearranging fields in database records. The memory is separated into modules, each module separately addressable. Each memory module is addressed by selectively modifying a supplied address, for example by the output from exclusive-OR gates, having inputs from the address supplied to the memory system and another inputs from address modification registers. The address modification registers are selectively set by the external utilization device to permit reading different rows in the memory modules. The data output columns from the memory modules can be rearranged using selector devices such as demultiplexors. Data can be masked by precluding certain selector control signals.