Abstract: Logical tracks having a constant capacity are composed of combinations of physical tracks in a plurality of disks. For example, in a case where the data recording region of the first disk is divided into three zones A, B, C and that of the second disk is divided into three zones A', B', C', the physical tracks of outer zone A and inner zone C', middle zones B and B' and inner zone C and outer zone A' are combined, respectively. A host apparatus issues a read/write command by using a logical track address, and a track address converter converts the logical track address into a plurality of physical track addresses. A magnetic disk controlling apparatus writes the entire part of a record instructed to be written by the host apparatus in a physical track in one magnetic disk apparatus, or splits the record into two portions and consecutively writes them into physical tracks of both magnetic disks.

Abstract: A processor includes an alias unit having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries that consist of a base address in the processor memory to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor can optionally include a data cache and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

Abstract: A system for writing to a cache memory which eliminates the need, in certain circumstances, to set a dirty bit. The dirty bit indicates that the line of data in the cache has been updated but the corresponding data in main memory has not been updated. Setting the dirty bit can increase the time needed for a bus cycle. When a line of data is written to a cache memory, a dirty bit is set for that line of data. If the next bus cycle is a write to the cache for the same line of data, the cache controller can save time by not setting the dirty bit because the cache controller knows that the dirty bit has been previously set.

Abstract: The present invention sets a first boot record indicating a first file group information on a head address of a non-volatile memory a second boot record indicating a second file group information on an end address of the non-volatile memory without partitioning the non-volatile memory. When accessing to files of first file group, an address is generated based on information on the first boot record. When accessing to files of second file group, an address is generated based on information on the second boot record.

Abstract: Each semiconductor memory module is divided into a plurality of access control units, and a service adapter copies the contents of the memory of the semiconductor memory module in which a memory error has occurred, to a spare semiconductor memory module one access control unit at a time. It is thus possible to evacuate the contents of the memory of the semiconductor memory module in which the memory error has occurred without stopping the semiconductor disk apparatus simply by adding the spare semiconductor disk apparatus. Since the copying operation is executed one access control unit at a time, a resource manager can conduct exclusive control also one access control unit at a time. A host apparatus therefore can access an access control unit portion which is not the object of copying even in the process of copying. In other words, the copying operation exerts no deleterious influence on the access of the host apparatus.

Abstract: A memory interface apparatus includes a plurality of data memories MEMs, and address modification units AMDs and memory access units I/Fs respectively corresponding to the plurality of data memories MEMs. Each address modification unit AMD has an offset table OFT for pre-storing a plurality of offsets, reads an offset from the table OFT based on received second data D2, modifies an address indicated by a received generation number GN using the read offset, and applies a resultant address to a corresponding memory access unit I/F. Each memory access unit I/F accesses a memory MEM based on the applied address, according to a received operation code C. Each result of access is applied in parallel to an operation unit ALU, which in turn performs operation of the applied result according to an operation code C. Thus, operation processing which compounds access to a memory can be carried out, utilizing parallelism in processing sufficiently.

Abstract: A computer architecture where a processor with store-through cache is linked with a cache control module, a bus interface to dual system busses, a system spy module monitoring the dual system busses for new data overwrites and an invalidation queue for holding cache addresses to be invalidated while the entire network is controlled by a programmable state machine system for enabling cache access and cache invalidation operations.

Abstract: A "wrapped-line" direct-mapped cache is disclosed that stores words with main-memory addresses that succeed a requested address where a conventional nonwrapped direct-mapped line-unit cache would store words with main-memory addresses that precede the requested memory address. Since succeeding addresses are more likely to be called "soon" after a requested address, the wrapped-line direct-mapped cache provides more efficient use of cache capacity, and thus more effectively enhances the performance of an incorporating system. The wrapped-line direct-mapped cache has indexed storage locations. Each storage location has sections for storing a tag, a string-boundary indicator, and a line of words. Each storage location has a line index, and each word position in a line has a word-position index. To determine whether a requested address results in a hit or a miss, the match logic divides the requested address into high, intermediate, and low segments.

Abstract: A non-fault-only (NFO) bit is included in the translation table entry for each page. If the NFO bit is set, non-faulting loads accessing the page will cause translations to occur. Any other access to the non-fault-only page is an error, and will cause the processor to fault. A non-faulting load behaves like a normal load except that it never produces a fault even when applied to a page with the NFO bit set. The NFO bit in a translation table entry marks a page that is mapped for safe access by non-faulting loads, but can still cause a fault by other, normal accesses. The NFO bit indicates which pages are illegal. Selected pages, such as the virtual page 0x0, can be mapped in the translation table. Whenever a null-pointer is dereferenced by a non-faulting load, a translation lookaside buffer (TLB) hit will occur, and zero will be returned immediately without trapping to software to find the requested page.

Abstract: A memory management unit (MMU) includes a translation lookaside buffer capable of simultaneously servicing three requests supplied to the MMU by an instruction cache and two data caches, respectively. Also, an arbiter selects one of several pending requests from sources of different priorities for immediate processing by the MMU, using a process which avoids undue delay in servicing requests from sources of lower priority.

Abstract: An apparatus including address generation units, corresponding reservation stations, and a speculative register file is provided. Decode units provide memory operation information to the corresponding reservation stations while the associated instructions are being decoded. The speculative register file stores speculative register values corresponding to previously decoded instructions. The speculative register values are generated prior to execution of the previously decoded instructions. If the register operands included in the address operands of an instruction are stored in the speculative register file, then the memory operation may be passed through the corresponding reservation station to an address generation unit. The address generation unit generates the data address from the address operands and accesses a data cache while register operands corresponding to the instruction are requested from a register file and reorder buffer.

Abstract: The disclosed is an DRAM which is accessible in response to four-state address signal. A two-state address signal generator receives the four-state address signal respectively defined by four voltage levels and converts it to a row address signal and a column address signal which are two-state address signals. Converted address signals are supplied to a row decoder and a column decoder, respectively. Address signals for access are supplied without adopting an address multiplexing system, so that it is possible to perform accurate addressing under the requirement of high speed operation. In addition, the number of sense amplifiers to be activated in one read operation can be reduced, and therefore power consumption can be also reduced.

Abstract: An apparatus for generating an address to increase efficiency in parallel processing in a multiprocessor system. A global address generating unit is provided within a vector unit of each of processing elements (PE) constituting a parallel computer system. An adder provided within the global address generating unit sequentially adds an increment of an address, d.sub.-- Adr.sub.-- exl, and d.sub.-- Adr.sub.-- in to an address Adr.sub.-- exl and Adr.sub.-- in, respectively. A subtracter outputs a quotient obtained by dividing d.sub.-- Adr.sub.-- exl by band width bexl as a logical PE number. Additionally, a remainder obtained as an output from a subtracter is added to Adr.sub.-- in, thereby enabling a logical in-PE address to be obtained. The logical PE number and the logical in-PE address thus obtained are converted to a real PE number and a real in-PE address. Generating a global address by hardware reduces overhead incurred by parallel operation of array data.

Abstract: An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a semiconductor device under test during a test process in real time and generates column addresses for the device under test by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, Z address signal, and an operation mode control signal is arranged, a conversion memory that outputs certain conversion table contents is arranged, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with the burst length control signal.

Abstract: By overlaying two memory banks to form a single, monolithic memory and setting a movable boundary point between those two banks, one can exceed the fixed addressing capability of a microprocessor. By moving the boundary, one can then access common-value memory locations in one or the other of the memory regions. The manipulation of the boundary can be performed by a microprocessor.

Abstract: In a data processing unit having a plurality of general purpose registers, an instruction is loaded. Such an instruction includes an operation, and at least one operand field, where the operand field specifies one of a plurality of base registers and a displacement value. To calculate a general purpose register address specified by such an operand field, the displacement value is added to a base value stored in a base register that is specified by a portion of the operand field. Finally, the data processing unit addresses a selected one of the general purpose registers, utilizing the calculated general purpose register address, for execution of the specified operation. Thus, the data processing unit is capable of addressing a larger number of general purpose registers than may be directly addressed utilizing a value represented by a limited number of bits within the operand field.

Abstract: A method of improving the performance of a computer processor by recognizing that two consecutive register instructions can be executed simultaneously and executing the two instructions simultaneously while generating a single data address and while performing exception checking on a single data address. During an instruction fetch process, two consecutive instructions are tested to determine if both are either register load instructions or register save instructions. If both instructions are load or save register instructions, the corresponding data addresses are tested to see if both data addresses are in the same double word. If both data addresses are in the same double word, then the instructions are executed simultaneously. Only one data address generation is required and exception processing is performed on only one data address.

Abstract: Log memories for recording updated history of a main memory are provided. CPUs record the updated history of the main memory to either of the log memories and writes context thereof and content of a cache memory to the main memory at a checkpoint acquisition. The updated history of the main memory is switched from one of CPUs that has finished a checkpoint processing to other one of the log memories in which the CPUs do not use to record the updated history of the main memory. Normal processing is restarted without waiting for finishing the checkpoint acquisition of the other ones of CPUs.

Abstract: By providing a digital video memory arrangement with first and second address generating circuits, digital video signals can be written at a first location of a non-mechanical memory and (almost) immediately read out from a second location of the non-mechanical memory, with the reading out both being capable of featuring backward and forward jumps. As a consequence of a coupling between the first and the second address generating circuits it becomes impossible to, on the one hand, unjustly pass with jumping in the read signal the running or stopped write signal and, on the other hand, unjustly pass with the running read signal the stopped write signal. To this end the second address generating circuits dispose over determining circuits for determining, in response to at least the write signal and the read signal, a permitted address jump.

Abstract: An apparatus is provided, including one or more early address generation units which attempt to perform data address generation upon decode of an instruction which includes a memory operand. The early address generation units may be successful at generating the data address if the logical data address is formed from a displacement only. Additionally, the early address generation unit may be successful at generating the data address if the logical data address is formed from the displacement and register operands which are available upon decode of the instruction. Data address generation latency may be shortened. If register operands are employed for forming the address and the register operands are not available, the data address may be generated in a functional unit at the execute stage.