Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive layer positioned on the substrate; at least one bottom conductive protrusion positioned on the bottom conductive layer; an insulator layer positioned on the bottom conductive layer and the at least one bottom conductive protrusion; at least one bottom insulating protrusion protruding from the insulator layer towards the bottom conductive layer and adjacent to the at least one bottom conductive protrusion; and a top conductive layer positioned on the insulator layer. The bottom conductive layer, the at least one bottom conductive protrusion, the insulator layer, the at least one bottom insulating protrusion, and the top conductive layer together configure a capacitor structure.

Abstract: The present application discloses a method for fabricating a semiconductor device with capacitors having a shared electrode. The method includes providing a substrate, forming a first trench in the substrate, doping sidewalls and a bottom surface of the first trench to form a bottom conductive structure, forming a first insulating layer on the bottom conductive structure and in the first trench, forming a shared conductive layer on the first insulating layer, forming a second insulating layer on the shared conductive layer, forming a top conductive layer on the second insulating layer, and forming a connection structure electrically connecting the bottom conductive structure and the top conductive layer. The bottom conductive structure, the first insulating layer, and the shared conductive layer together configure a first capacitor unit. The shared conductive layer, the second insulating layer, and the top conductive layer together configure a second capacitor unit.

Abstract: A semiconductor package assembly having a connecting clip disposed on both a first material stack and a second material stack having different thicknesses and disposed on a conducting substrate. This connecting clip has a first portion disposed on to the first material stack and second portion disposed on the second material stack, such that the surfaces of the first portion and second portion opposite the conducting substrate are at the same perpendicular distance from the conducting substrate. For example, in some implementations, when the thickness of the second material stack is smaller than the thickness of the first material stack, the second portion of the connecting clip may include a vertical support disposed on the second material stack to equalize the heights of the surfaces of the first portion and second portion of the connecting clip.

Abstract: An interconnect structure including a top via with a minimum line end extension comprises a cut filled with an etch stop material. The interconnect structure further comprises a line formed adjacent to the etch stop material. The interconnect structure further comprises a top via formed on the line adjacent to the etch stop material, wherein the top via utilizes the etch stop material to achieve minimum line extension.

Abstract: Some embodiments of the present disclosure relate to a semiconductor structure including a first conductive wire disposed over a substrate. A dielectric liner is arranged along sidewalls and an upper surface of the first conductive wire and is laterally surrounded by a first dielectric layer. The dielectric liner and the first dielectric layer are different materials. A conductive via is disposed within a second dielectric layer over the first conductive wire. The conductive via has a first lower surface disposed over the first dielectric layer and a second lower surface below the first lower surface and over the first conductive wire.

Abstract: Semiconductor devices and methods of forming conductive lines in the same include forming a cut region in a first dielectric layer, the cut region having a first width. A second dielectric plug is formed in the cut region. A mask is formed, over the first dielectric layer, that defines at least one trench region that crosses the second dielectric plug, with the at least one trench region having a second width that is smaller than the first width. Material from the first dielectric layer in the trench regions is etched away, using a selective anisotropic etch that leaves the second dielectric plug in place, to form trenches in the first dielectric layer. Conductive material is deposited in the trenches to form conductive lines that are separated by the second dielectric plug.

Abstract: An electronic device and method of fabricating the same are provided herein. The electronic device includes a first main pad; a second main pad; a first repair line electrically connected to the first main pad; a second repair line electrically connected to the second main pad, wherein the first repair line and the second repair line forms a first weldable region; a first spare pad; a second spare pad; a connection line electrically connected to the second repair line, the first spare pad and the second spare pad; and a first electronic unit disposed on the first main pad and the second main pad.

Abstract: A highly reliable display device. A first flexible substrate and a second flexible substrate overlap each other with a display element positioned therebetween. Side surfaces of at least one of the first substrate and the second substrate which overlap each other are covered with a high molecular material having a light-transmitting property. The high molecular material is more flexible than the first substrate and the second substrate.

Abstract: A full-color light emitting diode (LED) display having an improved luminance is provided herein. More specifically, provided herein are a full-color LED display, in which an amount of light blocked by electrodes and not extracted is minimized and ultra-small LED devices are connected to ultra-small electrodes without defects such as electrical short circuits and the like, wherein the full-color LED display exhibits a further improved luminance when a direct current (DC) driving voltage is used and each pixel of the full-color LED display exhibits uniform luminance when the DC driving voltage is used, and a method of manufacturing the same.

Abstract: A display device is capable of improving luminous efficiency and display quality and includes: a substrate; a thin film transistor on the substrate; a first electrode on the substrate and connected to the thin film transistor; a second electrode on the substrate and spaced apart from the first electrode; a plurality of light emitting elements between the first and second electrodes and electrically connected to each of the first and second electrodes; an insulating layer on the plurality of light emitting elements; and a reflective layer on the insulating layer. Each of the plurality of light emitting elements includes: a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer.

Abstract: A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.

Abstract: A semiconductor structure and a manufacturing method for the same. The semiconductor structure includes a plug element and a via element. The plug element includes a tungsten plug. The plug element has a plug size in a lateral direction. The via element is electrically connected on the plug element. The via element is non-symmetrical with respect a center line of the plug element extending along a longitudinal direction. The via element has a via size in the lateral direction. The plug size is bigger than the via size.

Abstract: A semiconductor device includes a fin structure, a two-dimensional (2D) material channel layer, a ferroelectric layer, and a metal layer. The fin structure extends from a substrate. The 2D material channel layer wraps around at least three sides of the fin structure. The ferroelectric layer wraps around at least three sides of the 2D material channel layer. The metal layer wraps around at least three sides of the ferroelectric layer.

Abstract: A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

Abstract: A method includes forming a first electrode layer having a first opening, with the first opening having a first lateral dimension, forming a first capacitor insulator over the first electrode layer, and forming a second electrode layer over the first capacitor insulator, with the second electrode layer having a second opening. The first opening is directly underlying the second opening. The second opening has a second lateral dimension greater than the first lateral dimension. The method further includes depositing a dielectric layer over the second electrode layer, and forming a contact opening, which comprises a first portion including the first opening, and a second portion including the second opening. A conductive plug is formed in the contact opening.

Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

Abstract: Described are ferroelectric device film stacks which include a templating or texturing layer or material deposited below a ferroelectric layer, to enable a crystal lattice of the subsequently deposited ferroelectric layer to template off this templating layer and provide a large degree of preferential orientation despite the lack of epitaxial substrates.

Abstract: A semiconductor storage device and an electronic device that include a ferroelectric capacitor having a more optimized structure, as a memory cell are provided. A semiconductor storage device includes a field-effect transistor provided in an active region of a semiconductor substrate, a ferroelectric capacitor including a first capacitor electrode and a second capacitor electrode sandwiching a ferroelectric film, the first capacitor electrode being electrically connected to one of a source or a drain of the field-effect transistor, a source line electrically connected to the second capacitor electrode of the ferroelectric capacitor, and a bit line electrically connected to another one of the source or the drain of the field-effect transistor, in which a gate electrode of the field-effect transistor extends in a first direction across the active region, and the source line and the bit line extend in a second direction orthogonal to the first direction.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, a first well region of a first conductive type and a second well region of a second conductive type disposed in the substrate. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures are disposed in the first well region and arranged along a junction between the first well region and the second well region. The first dummy structures respectively include a first conductive region and a first doped region disposed between the first conductive region and the first doped region.