Abstract: A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

Abstract: A method for forming contacts applied to a CMOS image sensor includes: forming a transmission gate structure; performing source and drain ion implantation processes to form source and drain; forming auxiliary sidewalls on the outer sides of the gate sidewalls, the material of the auxiliary sidewalls being the same as the material of the adjacent gate sidewalls; sequentially forming a silicide block layer, a contact etch stop layer and an interlayer dielectric layer; defining source and drain contact regions; performing etching processes to remove the interlayer dielectric layer and the contact etch stop layer corresponding to the source and drain contact regions sequentially; etching the silicide block layer by adopting a predetermined etching selection ratio to form source and drain contacts, wherein the etching rate of the silicide block layer is higher than the etching rate of the auxiliary sidewalls in the process of etching the silicide block layer.

Abstract: The disclosure discloses a copper plating filling process method, comprising the steps of: forming a trench or a through-hole in a dielectric layer; forming a copper seed layer on an inner surface of the hole; allowing a waiting time after forming the copper seed layer and before performing a copper plating process, wherein during the waiting time, a surface of the copper seed layer is oxidized to form a copper oxide layer; performing a reduction process on the copper oxide layer; and filling a copper layer into the hole in the copper plating process afterwards. The copper oxide layer on the surface of the copper seed layer is reduced to copper in the reduction process, and wherein a thickness of the copper seed layers on the inner surface of the hole is uniform. The hole can be a trench or a through-hole.

Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.

Abstract: A semiconductor device includes a second insulating layer disposed on a substrate and that includes a first trench that extends in a first direction, a first via disposed in the first hole, a first interconnection layer disposed in the first trench on the first via and that has an upwardly upper region, and a third insulating layer disposed on the second insulating layer and that includes a second hole and a second trench connected to the second hole. The first trench has inclined side surfaces such that a width of the first trench increases in a direction toward the substrate, the second hole has inclined side surfaces such that a width of the second hole decreases in the direction toward the substrate, and a lower portion of the second hole is wider than an upper surface of the first interconnection layer.

Abstract: The present disclosure provides a capacitor structure and a method for manufacturing same. The capacitor structure includes: a substrate, a first capacitor contact layer, a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer, where the first capacitor contact layer is arranged on the substrate in an array manner, the bottom electrode layer surrounds a side wall of the first capacitor contact layer and extends in a direction of the first capacitor contact layer away from the substrate, the capacitor dielectric layer covers an upper surface of the substrate, a surface of the bottom electrode layer and an upper surface of the first capacitor contact layer, and the top electrode layer covers a surface of the capacitor dielectric layer.

Abstract: Described are ferroelectric device film stacks which include a templating or texturing layer or material deposited below a ferroelectric layer, to enable a crystal lattice of the subsequently deposited ferroelectric layer to template off this templating layer and provide a large degree of preferential orientation despite the lack of epitaxial substrates.

Abstract: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.

Abstract: A method of processing substrates, in one example microelectronic workpieces, is disclosed that includes forming a multi-layer metal hard mask (MHM) layer in which at least one lower layer of the multi-layer MHM is comprised of ruthenium (Ru). The Ru MHM layer may be an atomic layer deposition (ALD) Ru MHM layer formed over one or more underlying layers on a substrate. The ALD Ru MHM layer may be etched to provide a patterned ALD Ru MHM layer, and then the one or more underlying layers may be etched using, at least in part, the patterned ALD Ru MHM layer as a mask to protect portion of the one or more underlying layers. In one embodiment, at least one of the underlying layers is a hard mask layer.

Abstract: A method includes providing a first wafer including a first substrate, a first dielectric layer disposed over the first substrate and a first component formed within the first dielectric layer; providing a second wafer including a second substrate, a second dielectric layer disposed over the second substrate, and a second component formed within the second dielectric layer; removing a first portion of the first dielectric layer to form a first recess; removing a second portion of the second dielectric layer to form a second recess; disposing the second wafer over the first wafer to bond the first dielectric layer to the second dielectric layer; removing a third portion of the second substrate and the second dielectric layer to form a third recess coupled to the second recess; and disposing a conductive material to fill the first recess, the second recess and the third recess to form a conductive structure.

Abstract: The present application discloses method for fabricating a semiconductor device. The method includes providing a substrate; forming a word line trench in the substrate; conformally forming a first insulating layer in the word line trench and conformity forming a first barrier layer on the first insulating layer; conformally forming a first nucleation layer on the first barrier layer; performing a post-treatment to the first nucleation layer, wherein the post-treatment comprises a reducing agent comprising diborane and a tungsten-containing precursor; forming a first bulk layer on the first nucleation layer, wherein the first nucleation layer and the first bulk layer configure a first conductive layer; and performing a planarization process to turn the first insulating layer, the first barrier layer, and the first conductive layer into a word line insulating layer, a word line barrier layer, and a word line conductive layer, respectively and correspondingly.

Abstract: An inductor module and a method for fabricating the same are disclosed. The inductor module includes a substrate, a first inter-level dielectric layer, a plurality of second inter-level dielectric layers, a trench, and a first metal layer. The first inter-level dielectric layer is disposed on the substrate. The second inter-level dielectric layers are sequentially stacked on the first inter-level dielectric layer. The trench is disposed to penetrate at least two of the second inter-level dielectric layers. The first metal layer is disposed in the trench. The first metal layer has a top side surface and a bottom side surface opposite to each other. The top side surface is coplanar with an upper surface of the trench in the second inter-level dielectric layers. The bottom side surface is coplanar with a bottom surface of the trench in the second inter-level dielectric layers.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect structure over the substrate. The chip structure includes a conductive pad over the interconnect structure. The chip structure includes a passivation layer covering the interconnect structure and exposing the conductive pad. The chip structure includes a first etch stop layer over the passivation layer. The chip structure includes a first buffer layer over the first etch stop layer. The chip structure includes a second etch stop layer over the first buffer layer. The chip structure includes a device element over the second etch stop layer.

Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

Abstract: A light emitting device includes a substrate; a pattern of a plurality of protrusions protruding from the substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer, in which each of the protrusions includes a first layer formed integrally with the substrate and protruding from an upper surface of the base substrate; and a second layer provided on the first layer and formed of a material different from that of the first layer.

Abstract: Described are ferroelectric device film stacks which include a templating or texturing layer or material deposited below a ferroelectric layer, to enable a crystal lattice of the subsequently deposited ferroelectric layer to template off this templating layer and provide a large degree of preferential orientation despite the lack of epitaxial substrates.

Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer; first and second insulating layers in contact with the first semiconductor layer; a second semiconductor layer in contact with the first insulating layer; a third semiconductor layer in contact with the second insulating layer; a first conductor; a third insulating layer in contact with the first conductor; a fourth insulating layer provided between the second semiconductor layer and the third insulating layer; a first charge storage layer provided between the second semiconductor layer and the fourth insulating layer; and a fifth insulating layer provided between the second semiconductor layer and the first charge storage layer. The second semiconductor layer, the first conductor, the third to fifth insulating layers, and the first charge storage layer function as a first memory cell.

Abstract: A method of manufacturing a light-emitting element includes: providing a substrate, wherein the substrate includes a top surface with a first area and a second area; introducing a semiconductor material to form a first layer on the first area and a second layer on the second area, wherein the first layer includes a first crystal quality and the second layer includes a second crystal quality, the first crystal quality is different from the second crystal quality; and dicing the substrate along the second area.

Abstract: A substrate structure and a semiconductor package structure including the same are provided. The substrate structure includes a circuit layer and a dielectric structure. The circuit layer has a bottom surface and a top surface opposite to the bottom surface. The dielectric structure around the circuit layer. The dielectric structure covers a first part of the bottom surface of the circuit layer, and exposes a second part of the bottom surface and the top surface of the circuit layer. The dielectric structure exposes the top surface of the circuit layer. In addition, a method of manufacturing a semiconductor package structure is also provided.