Abstract: Data communications among electronic devices within a computer, including transmitting, from a transmitting device to a first translation device, data communications encoded according to an unreliable wireline data communications protocol; translating, by the first translation device, the data communications from the encoding of the unreliable wireline data communications protocol to an encoding of a reliable wireless data communications protocol; transmitting, by the first translation device to a second translation device, the data communications according to the reliable wireless data communications protocol; translating, by the second translation device, the data communications from the encoding of the reliable wireless data communications protocol to the encoding of the unreliable wireline data communications protocol; and transmitting, by the second translation device to a receiving device, the data communications according to the unreliable wireline data communications protocol.

Abstract: A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, where the Ethernet controllers are integrated within a single chip. A particular one of the integrated Ethernet controllers may be identified based on information within the received data. The particular one of the integrated Ethernet controllers may be granted access to a shared resource within the single chip. The access to the shared resource may be granted using at least one semaphore register within the shared resource. The particular one of the integrated Ethernet controllers may be granted access to the single bus interface. The information may include a bus identifier, a bus device identifier and/or a bus function identifier. The shared resource may include a nonvolatile memory (NVM).

Abstract: A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.

Abstract: A removable electronic circuit card having both a memory module with a non-volatile mass storage memory and a separate input-output module so that data transfers may be made through the input-output module directly to and from the mass storage memory in a direct memory access (DMA) type transfer when the card is inserted into the host system but without having to pass the data through the host system. Once the host gives a DMA command, the data transfer is accomplished independently of the host system, except for the host supplying power and possibly a clock signal and other like support, during such a data transfer directly with card. The data for the transfer can be communicated between the input-output module and the exterior device through either wireless or an electrical connection means.

Abstract: A multifunctional device shifts the states of plural reception units from a state that the device operates in a power saving state to a state that the device operates in an operating state, according to which of the plural reception units a reception request of data is input to. The multifunctional device can shorten a time from the reception of the reception request of the data to the reception unit to a start of a data process of the data.

Abstract: A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction.

Abstract: Systems and methods include a circuit for detecting the insertion of a component into a docking station, e.g., an audio plug. When the component is inserted into the docking station, an electronic switch can be opened. When the switch is opened, a detector (e.g., monostable multivibrator) for detecting a change in state of the switch can be activated. Responsive to the detected change in state, the detector can issue a signal to a control device. Responsive to the signal, the controller can look to a resistive identification circuit and, based on its resistance, determine whether the component has just been inserted or removed from the docking station.

Abstract: A scalable computer node includes a first central processing unit (CPU), a memory subsystem, and a socket that is configured to receive a second CPU. An expansion module is mounted in the socket instead of the second CPU, where the expansion module is socket-compatible with the second CPU. The expansion module has a CPU interface to communicate with the first CPU, a memory interface to communicate with the memory subsystem, and a fabric interface to communicate over a communications fabric with an expansion electronic subsystem to expand a capacity of the computer node.

Abstract: Power from a modular chassis to plural modular information handling systems contained by the chassis is dynamically allocated according to power consumed at each modular information handling system and a priority associated with each modular information handling system. A power manager of the modular chassis allocates power by setting a maximum power for each modular information handling system based upon a priority for each modular information handling system. A power monitor on a modular information handling system requests additional power allocation if power consumed is within a predetermined amount of the maximum power for that system. The power manager allocates additional power in response to the request if another modular information handling system has excess power allocated or if the requesting modular information handling system has a higher priority than another modular information handling system.

Abstract: A receive-side client interface for a media access controller embedded in an integrated circuit having programmable circuitry is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath is configured to operate at two frequencies to accommodate the programmable circuitry in the integrated circuit.

Abstract: A card-type peripheral device includes an electronic component including a memory disposed in a case, a terminal part including connection terminals connectable with a to-be-connected device, and a switch for disabling writing to the memory. The card-type peripheral device further includes a signal terminal capable of transmitting a signal indicating the status of the switch to the to-be-connected device.

Abstract: A media access system in an integrated circuit device having programmable resources for interfacing to a network. The media access system has at least one embedded media access controller configured to provide access to and from the network via a physical layer interface, programmable resources coupled to the embedded controller via a client interface, tie-off pin inputs coupled to the embedded controller for receiving a configuration vector for configuring the embedded controller without having to use a microprocessor for such configuration with the client interface being for communication between the embedded controller and the programmable resources for access to and from the network, and the embedded controller including a multi-mode interface coupled to the client interface for coupling to the programmable resources, the multi-mode interface including a plurality of Media Independent Interface modes, the multi-mode interface configured to be coupled to the physical layer interface.

Abstract: An information processing apparatus for communicating with an external apparatus via a predetermined communication interface including a data signal line and an insertion/removal signal line is provided. The information processing apparatus includes a processing unit for executing an application that a user desires, a communication controlling unit for controlling a communication operation using the predetermined communication interface, at least two communication connectors that comply with the predetermined communication interface, an analog switch for switching between each of the at least two communication connectors and the communication controlling unit, and an interface controlling unit for enabling the data signal line of one of the at least two communication connectors by switching connection to the data signal line using the analog switch so as to cause the communication controlling unit to perform communication with an external apparatus connected to the enabled communication connector.

Abstract: An interface circuit is disclosed. When a USB-BUS power source voltage VBUS is not normally supplied to the substrate gates of PMOS transistors of switches of a first switching circuit which controls connecting a terminal D+/RXD to a terminal D?/TXD in an HS driver circuit, and to the substrate gates of PMOS transistors of switches of a second switching circuit which controls connecting the terminal D+/RXD to the terminal D?/TXD in an FS driver circuit 6; an amplified core circuit power source voltage DVDD is supplied to the substrate gates of the PMOS transistors. When the USB-BUS power source voltage VBUS is normally supplied to the substrate gates of the PMOS transistors, a USB stabilized power source voltage VUSB is supplied to the substrate gates of the PMOS transistors.

Abstract: A method and apparatus for operating a portable computer configured for docking to a docking station is disclosed. In one embodiment, a portable computer system includes a docking interface having a bus switch and a bus monitoring circuit, and a bus coupled to the docking interface. With the computer coupled to a docking station, the bus switch, when closed, may couple the bus to a peripheral interface in the docking station. The bus switch may close responsive to docking, thereby completing the electrical coupling of the bus to the peripheral interface in the docking station. The portable computer being docked to the docking station, the bus monitoring circuit may monitor the bus cycles occurring on the bus and identify trusted read and/or write cycles.

Abstract: An apparatus includes a Universal Serial Bus (USB) transceiver of a USB host controller, a first pull-down resistor, a first switch, a second pull-down resistor, a second switch, and a detachment module. The USB transceiver has a differential output. The first switch electrically couples the first pull-down resistor to a positive terminal of the differential output in response to a first switch control signal. The second switch electrically couples the second pull-down resistor to a negative terminal of the differential output in response to a second switch control signal. The detachment module selectively determines whether a USB device is electrically coupled to the differential output by checking a voltage at the differential output while at least one of the first switch control signal or the second switch control signal is asserted.

Abstract: A data accessing system bridges a first master device and a second master device to a first slave device and a second slave device. The data accessing system includes a register, a first multiplexer, a second multiplexer and a control unit. The amount of data that the first master device can process each cycle is less than which of the second slave device. The data accessing system can solve the problem when the first master device writes data to the second slave device via merging two different data. Also, the data accessing system can solve the problem when the first master device reads data to the second slave device via extracting part of the data.

Abstract: Embodiments are generally directed to an apparatus for determining compatibility between devices. In one embodiment, a table including a module's parameters and rules associated therewith is obtained from a module. The rules are applied to a slot's parameters to determine the module's compatibility with the slot upon coupling to the slot.

Abstract: An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.

Abstract: An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.