Abstract: Resource information and status information concerning devices connected to a network is acquired and the information is stored in memory. Icons that are capable of identifying the types of devices connected to the network based upon the stored resource information and status of utilization of the devices that is based upon the stored status information are displayed in combination on a display unit. In order to select (S504, S505, S506) either one or both of the resource information and status information and update this information, a device for which information is to be updated is specified from among the displayed icons. Both the resource information and status information, or whichever information has been selected, of the device that has been specified is acquired and the information in memory is updated (S507) based upon this information.

Abstract: Disclosed is a device and method for performing a multi-function using a unique port in a wireless terminal capable of performing a multimedia function using the unique port. The device includes an interface unit for outputting a power signal through a connector inserted into the unique port, and performing data transmission/reception between a specific controller and the connector. A signal generating unit outputs a high-level signal by using the power signal output from the interface unit. A switching unit switches to a specific controller to communicate data with the connector, in order to output the high-level signal. At least two controllers include at least two transmission/reception units, for transmitting/receiving data to/from the connector through the switching unit.

Abstract: According to one embodiment, a system is disclosed. The system includes an initiator device to transmit input/output (I/O) write data and a target device, coupled to the initiator device, to receive the write data from the initiator device as a first segment of data and a second segment of data. The target device re-transmits a transfer ready frame to force the initiator device to retransmit the second segment in response to detecting an uncorrectable error in the second segment.

Abstract: A method and apparatus for efficient memory allocation and system management interrupt (SMI) handling is herein described. Upon waking a second processor in a multiple processor system, one may use a single SMI to initialize each processor, may use the location of a single default SMI handler as a wake-up vector to the second processor, and may patch an instruction pointer to a non-aligned address during the handling of the SMI with the second processor to forgo the traditional extra aligned memory allocation. In addition, one may use unified handler code to handle software generated SMIs on both the first and second processors and may use exit SMM directly after handling a hardware SMI to save execution time.

Abstract: An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.

Abstract: A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by a data bus chain having a number of data bus bits. The data bus chain has a first portion of data bus bits dedicated to transmitting write data from the memory controller to a memory chip. The data bus chain has a second portion of data bus bits dedicated to transmitting read data from a memory chip to the memory controller. Apportionment of data bus bits between the first portion and the second portion is programmable. Programming is done by pin connection, scanning of a value, or by request from a processor coupled to the memory controller.

Abstract: A host automated meter reading (AMR) device may communicate with one or more client AMR devices in proximity to the host meter. The host and client AMR devices operate as master and slave devices, respectively, in a host-client AMR device system. The host AMR device may transmit command and control functions to the client AMR devices, and may receive AMR device information from each client AMR device. The host AMR device may also transmit AMR device information from both itself and the client AMR devices over a communications network to a utility. Furthermore, the host AMR device may receive command and control functions from the utility via the same communications network, and may relay those functions to the AMR devices associated with that particular host AMR device.

Abstract: A media access controller system embedded in a programmable logic device is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in a programmable logic device. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.

Abstract: A computing hardware and software device called a Meta Mentor Central Processing Unit. The Meta Mentor purpose is to control memory, input/output interfaces, defining the operating system, the scheduling processes and the parsing of individual threads to an array of slave Processing Units that are uniquely connected, thus creating a highly optimized computing core. In effect, the Meta Mentor tells the array of slave processors what to process by controlling all external and internal system input/output and individual processor scheduling.

Abstract: An apparatus for linking a hot-plug device to a host includes a slave interface circuit for connection to the host; a master interface circuit for connection to the hot-plug device; and direction, data, and clock lines that link the master and slave interface circuits. A control logic circuit detects a Presence Detect signal on the direction line. A method of determining a connection between a host and a hot-plug device includes asserting a direction signal on a direction line to control a direction of a flow of data between the host and the hot-plug device; toggling the direction signal to indicate a presence of the hot-plug device; and indicating a disconnect after a given period of inactivity in the toggling. A method of linking a host and a hot-plug device interface circuit for connection to a hot-plug device includes asserting a Presence Detect signal on the direction line.

Abstract: A removable electronic circuit card has multiple modules connected to the card's bus in parallel so that each module can exchange commands and data independently with the host. According to a first aspect of the present invention, this achieved by a controller-to-controller interface whereby the modules can facilitate their interactions with the host. In a first set of embodiments, the modules are on a single card, while in a second set of embodiments the modules are distributed across multiple cards, where a first card attaches to the host and other cards attach to the first card rather than directly to the host. In all of these cases, the host sees the multiple modules as a single card having a single module. In a further aspect of the present invention, the card or cards are able to communicate with the host in more than one protocol.

Abstract: According to the present invention, there is provided a semiconductor device comprising: a power line to be externally supplied with a power supply voltage; a ground line for grounding; a first signal line for transmitting a first signal; a second signal line for transmitting a second signal; a first switching element and first resistance element connected in series between said first signal line and a power terminal which supplies a predetermined potential; a second switching element and second resistance element connected in series between said second signal line and said ground line; and a controller which is connected to said power line, said ground line, said first signal line, and said second signal line, and, when detecting that a potential of said power line has reached the power supply voltage, turns on said first switching element and said second switching element, and turns off said second switching element after an elapse of a predetermined time.

Abstract: Embodiments are generally directed to a method and apparatus for determining compatibility between devices. In one embodiment, a table including a module's parameters and rules associated therewith is obtained from a module. The rules are applied to a slot's parameters to determine the module's compatibility with the slot upon coupling to the slot.

Abstract: A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.

Abstract: A receive-side client interface for a media access controller embedded in an integrated circuit having programmable logic is described. A media access controller core includes a receive engine. A receive-side datapath is coupled to the media access controller core. The receive-side datapath configured is configured to operate at two frequencies to accommodate the programmable logic in the integrated circuit.

Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Abstract: In a portable FireWire compatible device, a direct memory access (DMA) bus switch coupled by way of a DMA bus to a central processing unit (CPU), a local hard drive (HDD), and a FireWire port, provides a direct connection between the FireWire port and the HDD bypassing a main bus and the CPU when a data transfer request is received and processed by the CPU. Otherwise, until the data transfer request is received and processed, the CPU is directly connected to the HDD. In this way, a high speed data transfer between the FireWire port and the HDD is provided only when an appropriate data transfer request is received and processed.

Abstract: An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.

Abstract: A method and system is provided for detecting excessive interrupt processing for a processor. The method includes the operation of defining an interrupt processing period during which measuring of interrupts for a processor takes place. The amounts of time being spent by the processor in an interrupt context can then be measured during the interrupt processing period. A further operation is detecting an interrupt storm occurring for the processor based on the amounts of time spent by the processor in interrupt context during the interrupt processing period.

Abstract: A bus bridge interfaces a primary-side bus with a plurality of secondary-side buses. The primary side bus is a local bus in a system and the secondary-side buses are external buses connected to the system. The bus bridge supports a plurality of kinds of operations one of which is an operation related to a serial bus in accordance with IEEE1394. An access right is given equally to each of the secondary-side buses, when access demands to the primary-side bus are lodged from more than two of the secondary side buses at the same time, by not giving a priority to any one of the secondary side buses.